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1.发明授权Serial scan chain architecture for a data processing system and method of operation 失效串行扫描链架构，用于数据处理系统和操作方法
公开(公告)号：US5592493A
公开(公告)日：1997-01-07
申请号：US304968
申请日：1994-09-13
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318536 , G01R31/318558
摘要： A scan chain architecture which has a controller (10), and a multiplexer (24) is used to route test data through functional units (12, 14, 16, 18, 20, and 22). The controller (10) receives as input a serial data stream from an STDI terminal and demultiplexes this data stream to one of the functional units (six functional units are illustrated in FIG. 1). Each of the functional units is considered as one scan chain and therefore FIG. 1 has six scan chains (one for each functional unit). In addition, a seventh scan chain couples all output flip-flops in each of the functional units together between an output of the MUX (24) and the STDO terminal/pin. Therefore, a serial scan of a data stream can be done through one functional unit, the multiplexer (24) and into the output flip-flops of each function unit to make testing easier to set-up. In addition, various new scan chain cells and low power methods are used herein.
摘要翻译： 具有控制器（10）和多路复用器（24）的扫描链架构用于通过功能单元（12,14,16,18,20和22）路由测试数据。 控制器（10）作为输入接收来自STDI终端的串行数据流，并将该数据流解复用于功能单元之一（图1中示出了六个功能单元）。 每个功能单元被认为是一个扫描链，因此， 1具有6个扫描链（每个功能单元一个）。 此外，第七扫描链将MUX（24）的输出和STDO端子/引脚之间的每个功能单元中的所有输出触发器耦合在一起。 因此，可以通过一个功能单元，多路复用器（24）和每个功能单元的输出触发器来完成数据流的串行扫描，以使测试更容易设置。 此外，在本文中使用各种新的扫描链单元和低功率方法。
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2.发明授权Data processing system for performing either a precise memory access or an imprecise memory access based upon a logical address value and method thereof 失效数据处理系统，用于基于逻辑地址值及其方法执行精确的存储器访问或不精确的存储器访问
公开(公告)号：US5666509A
公开(公告)日：1997-09-09
申请号：US216998
申请日：1994-03-24
申请人： Daniel M. McCarthy , Joseph C. Circello , Richard Duerden , Gregory C. Edgington , Cliff L. Parrott , William B. Ledbetter, Jr.
发明人： Daniel M. McCarthy , Joseph C. Circello , Richard Duerden , Gregory C. Edgington , Cliff L. Parrott , William B. Ledbetter, Jr.
CPC分类号： G06F12/0888 , G06F9/3861 , G06F12/0804 , G06F12/1027
摘要： A processor (10) has a data cache unit (16) wherein the data cache unit includes a memory management unit (MMU) (32). The MMU contains memory locations within transparent translation registers (TTRs), an address translation cache (40), or a table walk controller (42) which store or generate cache mode (CM) bits which indicate whether a memory access (i.e., a write operation) is precise or imprecise. Precise operations require that a first write operation or bus write instruction be executed with no other operationsnstructions executing until the first operation/instruction completes with or without a fault. Imprecise operations are operations/instruction which may be queued, partially performed, or execution simultaneously with other instructions regardless of faults or bus write operations. By allowing the logical address to determine whether the bus write operation is precise or imprecise, a large amount of system flexibility is achieved.
摘要翻译： 处理器（10）具有数据高速缓存单元（16），其中数据高速缓存单元包括存储器管理单元（MMU）（32）。 MMU包含存储或产生高速缓存模式（CM）位的透明转换寄存器（TTR），地址转换高速缓冲存储器（40）或表格移动控制器（42）内的存储单元，其指示存储器访问（即，写入 操作）精确或不准确。 精确的操作要求执行第一个写入操作或总线写入指令，直到第一个操作/指令完成或不存在故障，才执行其他操作/指令。 不精确的操作是可以与其他指令同时排队，部分执行或执行的操作/指令，而不管故障或总线写操作。 通过允许逻辑地址来确定总线写操作是精确还是不准确，实现了大量的系统灵活性。
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3.发明授权Superscalar processor with plural pipelined execution units each unit selectively having both normal and debug modes 失效超标量处理器具有多个流水线执行单元，每个单元选择性地具有正常和调试模式
公开(公告)号：US5530804A
公开(公告)日：1996-06-25
申请号：US242767
申请日：1994-05-16
IPC分类号： G06F11/26 , G06F11/267 , G06F11/36
CPC分类号： G06F11/3648 , G06F11/2236 , G06F11/261 , G06F12/10
摘要： A processor (10) has two modes of operation. One mode of operation is a normal mode of operation wherein the processor (10) accesses user address space or supervisor address space to perform a predetermined function. The other mode of operation is referred to as a debug, test, or emulator mode of operation and is entered via an exception/interrupt. The debug mode is an alternate operational mode of the processor (10) which has a unique debug address space which executes instructions from the normal instruction set of the processor (10). Furthermore, the debug mode of operation does not adversely affect the state of the normal mode of operation while executing debug, test, and emulation commands at normal processor speed. The debug mode is totally non-destructive and non-obtrusive to the "suspended" normal mode of operation. While in debug mode, the existing processor pipelines, bus interface, etc. are utilized.
摘要翻译： 处理器（10）具有两种操作模式。 一种操作模式是正常操作模式，其中处理器（10）访问用户地址空间或管理员地址空间以执行预定功能。 其他操作模式被称为调试，测试或仿真器操作模式，并通过异常/中断输入。 调试模式是处理器（10）的替代操作模式，其具有独特的调试地址空间，其执行来自处理器（10）的正常指令集的指令。 此外，在以正常的处理器速度执行调试，测试和仿真命令时，调试操作模式不会对正常操作模式的状态产生不利影响。 调试模式是完全非破坏性的，不违反“暂停”正常操作模式。 在调试模式下，利用现有的处理器管线，总线接口等。
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4.发明授权Decryption systems and related methods for on-the-fly decryption within integrated circuits 有权解密系统及相关方法用于集成电路内的即时解密公开(公告)号：US09418246B2
公开(公告)日：2016-08-16
申请号：US14570706
申请日：2014-12-15
CPC分类号： G06F21/72 , G09C1/00 , H04L9/0637
摘要： Methods and systems are disclosed for on-the-fly decryption within an integrated circuit that adds zero additional cycles of latency within the overall decryption system performance. A decryption system within a processing system integrated circuit generates an encrypted counter value using an address while encrypted code associated with an encrypted software image is being obtained from an external memory using the address. The decryption system then uses the encrypted counter value to decrypt the encrypted code and to output decrypted code that can be further processed. A secret key and an encryption engine can be used to generate the encrypted counter value, and an exclusive-OR logic block can process the encrypted counter value and the encrypted code to generate the decrypted code. By pre-generating the encrypted counter value, additional cycle latency is avoided. Other similar data independent encryption/decryption techniques can also be used such as output feedback encryption/decryption modes.
摘要翻译： 公开了用于集成电路内的即时解密的方法和系统，其在整个解密系统性能中增加零个额外的延迟周期。 处理系统集成电路内的解密系统使用地址生成加密的计数器值，而使用该地址从外部存储器获得与加密的软件映像相关联的加密代码。 解密系统然后使用加密的计数器值来解密加密的代码并输出可进一步处理的解密代码。 可以使用秘密密钥和加密引擎来生成加密的计数器值，并且异或逻辑块可以处理加密的计数器值和加密的代码以生成解密的代码。 通过预生成加密的计数器值，避免了额外的周期延迟。 还可以使用其他类似的数据独立加密/解密技术，例如输出反馈加密/解密模式。
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5.发明授权公开(公告)号：US09116845B2
公开(公告)日：2015-08-25
申请号：US13033327
申请日：2011-02-23
CPC分类号： G06F12/1416 , G06F21/62
摘要： A system and method are disclosed for determining whether to allow or deny an access request based upon one or more descriptors at a local memory protection unit and based upon one or more descriptors a system memory protection unit. When multiple descriptors of a memory protection unit apply to a particular request, the least-restrictive descriptor will be selected. System access information is stored at a cache of a local core in response to a cache line being filled. The cached system access information is merged with local access information, wherein the most-restrictive access is selected.
摘要翻译： 公开了一种用于基于本地存储器保护单元上的一个或多个描述符并且基于一个或多个描述符来确定系统存储器保护单元来确定是允许还是拒绝访问请求的系统和方法。 当存储器保护单元的多个描述符适用于特定请求时，将选择最小限制描述符。 响应于正在填充的高速缓存行，将系统访问信息存储在本地核心的高速缓存中。 缓存的系统访问信息与本地访问信息合并，其中选择最严格的访问。
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公开(公告)号：US06766433B2
公开(公告)日：2004-07-20
申请号：US09957780
申请日：2001-09-21
IPC分类号： G06F1210
摘要： A system (10) implements user programmable addressing modes in response to control information contained within an input address. Encoded control information stored in a plurality of user programmed address permutation control registers (70-72) is used to determine what bit values are used to replace predetermined bits of the input address to selectively create a corresponding permutated address. Since no modification to a processor's pipeline is required, various permutation addressing modes may be user-defined and implemented using either a general-purpose processor or a specialized processor.
摘要翻译： 系统（10）响应于包含在输入地址内的控制信息来实现用户可编程寻址模式。 存储在多个用户编程的地址置换控制寄存器（70-72）中的编码控制信息用于确定使用什么位值来替换输入地址的预定位以选择性地创建相应的置换地址。 由于不需要修改处理器的流水线，因此可以使用通用处理器或专用处理器来对用户定义和实现各种置换寻址模式。
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公开(公告)号：US4928225A
公开(公告)日：1990-05-22
申请号：US240747
申请日：1988-09-02
CPC分类号： G06F12/0866 , G06F12/0831 , G06F12/0848 , G06F12/1054 , G06F12/0835
摘要： A multiprocessing system includes a cache coherency technique that ensures that every access to a line of data is the most up-to-date copy of that line without storing cache coherency status bits in a global memory and any reference thereto. An operand cache includes a first directory which directly, on a one-to-one basis maps a range of physical address bits into a first section of the operand cache storage. An associative directory multiply maps physical addresses outside of the range into a second section of the operand cache storage section. All stack frames of user programs to be executed on the time-shared basis are stored in the first section, so cache misses due to stack operations are avoided. An instruction cache haivng various categories of instructions stores a group of status bits identifying the instruction category with each instruction. When a context switch occures, only instructions of the category least likely to be used in the near future are cleared decreasing delays due to clearing of the instruction cache as a result of context switches. A page-mapped I/O cache structure interfaces by a large number of I/O channels which regard a single I/O cache as an exclusive buffer. System operating delays due to maintaining cache coherency, operand cache misses, instruction cache misses, I/O cache misses, and maintaining a cache coherency are substantially reduced.
摘要翻译： 多处理系统包括高速缓存一致性技术，其确保对一行数据的每次访问是该行的最新的副本，而不将高速缓存一致性状态位存储在全局存储器中以及对其的任何引用。 操作数缓存包括直接在一对一的基础上将物理地址位的范围映射到操作数高速缓冲存储器的第一部分中的第一目录。 关联目录乘法将物理地址超出范围的映射映射到操作数高速缓存存储部分的第二部分。 要在时间共享的基础上执行的所有用户程序的堆栈帧被存储在第一部分中，因此避免了由于堆栈操作导致的高速缓存未命中。 各种类别的指令的指令高速缓存存储一组标识每个指令的指令类别的状态位。 当发生上下文切换时，由于由于上下文切换而导致指令高速缓存清除，所以仅在最近将来可能使用的类别的指令被清除减少延迟。 页面映射的I / O缓存结构由大量I / O通道接口，将单个I / O缓存视为独占缓冲区。 由于维护高速缓存一致性，操作数高速缓存未命中，指令高速缓存未命中，I / O高速缓存未命中以及维护高速缓存一致性引起的系统运行延迟大大降低。
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8.发明授权
公开(公告)号：US4506340A
公开(公告)日：1985-03-19
申请号：US481684
申请日：1983-04-04
IPC分类号： G06F7/72
CPC分类号： G06F7/722
摘要： Method and apparatus for producing the residue of the product of a multiplier and a multiplicand where the multiplier, multiplicand and product are residues with respect to a check base m, and where m=(2.sup.b -1) and b is the number of bits in a residue. An addressable memory device has at least 2 2(b-1) memory locations with each memory location having an address of 2 (b-1) bits. The address of each memory location can be considered as having two components each of (b-1) bits. The residue stored at each addressable location of the device is the residue of the product of the two components of its address. In response to each address being applied to the memory device, the residue of the product of the two components stored at the addressed memory location is read out of the device. The lower order (b-1) bits of the multiplier is applied to the device if the most significant bit of the multiplier is a logical zero. If the most significant bit of the multiplier is a logical one, the complement of the lower order (b-1) bits is applied and forms one component of the address of a memory location of the device. Similarly, the value of the most significant bit of the multiplicand determines whether the lower order (b-1) bits of the multiplicand or their complements form the other component of the address applied to the memory device. The residue read out of the addressed location is complemented to produce the residue of the product stored at the addressed memory location if and only if one of the most significant bits of the multiplier and multiplicand is a logical one, otherwise the residue read out of the memory device is the residue of the product of the multiplier and the multiplicand.
摘要翻译： 用于产生乘法器和乘法器的乘积残差的方法和装置，其中乘法器，被乘数和乘积相对于校验位m是残差，并且其中m =（2b-1）和b是位数 一个残留物 可寻址存储器件具有至少2 2（b-1）个存储器位置，每个存储器位置具有2（b-1）位的地址。 每个存储器位置的地址可以被认为具有每个（b-1）位的两个分量。 存储在设备的每个可寻址位置的残留物是其地址的两个组件的乘积的残留物。 响应于将每个地址应用于存储器设备，存储在寻址的存储器位置的两个组件的乘积的残差从设备中读出。 如果乘法器的最高有效位为逻辑0，则乘法器的低阶（b-1）位被施加到器件。 如果乘法器的最高有效位是逻辑1，则应用较低阶（b-1）位的补码，并且形成设备的存储器位置的地址的一个分量。 类似地，被乘数的最高有效位的值确定被乘数或其补码的低阶（b-1）位是否构成应用于存储器件的地址的另一分量。 补充了从寻址位置读出的残差，以产生存储在寻址的存储器位置的产品的剩余，如果且仅当乘法器和被乘数中的最高有效位之一是逻辑1，否则从 存储器件是乘法器和被乘数乘积的残差。
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9.发明授权
公开(公告)号：US4151510A
公开(公告)日：1979-04-24
申请号：US900627
申请日：1978-04-27
CPC分类号： H03M13/17
摘要： In an information handling system in which a cyclic code is utilized to both detect and correct errors and a cyclical redundancy code is used for supplementary detection of errors, the cyclical redundancy code (CRC) polynomial is chosen to be a factor of the generator polynomial, g(x), of the error detection and correction (EDAC) code. In this way, the same check bits in the code word used for error detection and correction may be further utilized for a CRC check to supplement the error detection capabilities of the system. The risk of miscorrection of data is reduced to de minimus levels by the partitioning of data and count fields in the course of the development of the error detection and correction codes. Practice of the teachings herein disclosed provides a more efficient error detection and correction system with greatly reduced risk of miscorrection. An embodiment of the invention is disclosed following the methodology taught herein.
摘要翻译： 在利用循环码来检测和纠正错误的信息处理系统中，循环冗余码被用于补充检测错误，循环冗余码（CRC）多项式被选择为生成多项式的因子， g（x），错误检测和校正（EDAC）代码。 以这种方式，用于错误检测和校正的代码字中的相同校验位可以进一步用于CRC校验以补充系统的错误检测能力。 错误检测和校正码开发过程中数据分割和计数字段的数据误差风险降低到最小级别。 本文公开的教导的实践提供了一种更有效的错误检测和校正系统，其大大降低了错误修复的风险。 根据本文教导的方法公开本发明的实施例。
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公开(公告)号：US09729319B2
公开(公告)日：2017-08-08
申请号：US14570611
申请日：2014-12-15
CPC分类号： H04L9/0894 , H04L9/0822 , H04L2209/12
摘要： Methods and systems are disclosed for key management for on-the-fly hardware decryption within an integrated circuit. Encrypted information is received from an external memory and stored in an input buffer within the integrated circuit. The encrypted information includes one or more encrypted key blobs. The encrypted key blobs include one or more secret keys for encrypted code associated with one or more encrypted software images stored within the external memory. A key-encryption key (KEK) code for the encrypted key blobs is received from an internal data storage medium within the integrated circuit, and the KEK code is used to generate one or more key-encryption keys (KEKs). A decryption system then decrypts the encrypted key blobs using the KEKs to obtain the secret keys, and the decryption system decrypts the encrypted code using the secret keys. The resulting decrypted software code is then available for further processing.
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