公开(公告)号：US09000558B2

公开(公告)日：2015-04-07

申请号：US12534640

申请日：2009-08-03

申请人： Ali Sarfaraz ,  Arya Reza Behzad

发明人： Ali Sarfaraz ,  Arya Reza Behzad

IPC分类号： H01L23/485 ,  H01L23/522 ,  H01L23/31

CPC分类号： H01L23/5227 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/5223 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2924/0002 ,  H01L2224/05552

摘要： A packaged integrated circuit includes an integrated circuit having a Radio Frequency (RF) passive element formed therein and a wafer level chip scale flip chip package that contains the integrated circuit. The wafer level chip scale flip chip package includes at least one dielectric layer isolating a top metal layer of the integrated circuit and a package signal connection upon the at least one dielectric layer, wherein the package signal connection partially overlays the RF passive element with respect to a surface of the integrated circuit. The RF passive element may be an inductor, a transformer, a capacitor, or another passive element. The package signal connection may be a conductive ball, a conductive bump, a conductive pad, or a conductive spring, for example. A conductive structure may reside upon the at least one dielectric layer to provide shielding to the RF passive element and may include a plurality of conductive elements or a mesh.

摘要翻译： 封装的集成电路包括其中形成有射频（RF）无源元件的集成电路和包含集成电路的晶片级芯片级倒装芯片封装。 晶片级芯片尺寸倒装芯片封装包括隔离集成电路的顶部金属层和至少一个电介质层上的封装信号连接的至少一个电介质层，其中封装信号连接部分地覆盖RF无源元件相对于 集成电路的表面。 RF无源元件可以是电感器，变压器，电容器或另一无源元件。 封装信号连接例如可以是导电球，导电凸块，导电垫或导电弹簧。 导电结构可以位于至少一个电介质层上，以提供对RF无源元件的屏蔽，并且可以包括多个导电元件或网状物。

公开(公告)号：US20100181642A1

公开(公告)日：2010-07-22

申请号：US12534640

申请日：2009-08-03

申请人： Ali Sarfaraz ,  Arya Reza Behzad

发明人： Ali Sarfaraz ,  Arya Reza Behzad

IPC分类号： H01L23/52 ,  H01L27/06

CPC分类号： H01L23/5227 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/5223 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2924/0002 ,  H01L2224/05552

摘要： A packaged integrated circuit includes an integrated circuit having a Radio Frequency (RF) passive element formed therein and a wafer level chip scale flip chip package that contains the integrated circuit. The wafer level chip scale flip chip package includes at least one dielectric layer isolating a top metal layer of the integrated circuit and a package signal connection upon the at least one dielectric layer, wherein the package signal connection partially overlays the RF passive element with respect to a surface of the integrated circuit. The RF passive element may be an inductor, a transformer, a capacitor, a transistor, or another passive element. The package signal connection may be a conductive ball, a conductive bump, a conductive pad, or a conductive spring, for example. A conductive structure may reside upon the at least one dielectric layer to provide shielding to the RF passive element and may include a plurality of conductive elements or a mesh.

摘要翻译： 封装的集成电路包括其中形成有射频（RF）无源元件的集成电路和包含集成电路的晶片级芯片级倒装芯片封装。 晶片级芯片尺寸倒装芯片封装包括隔离集成电路的顶部金属层和至少一个电介质层上的封装信号连接的至少一个电介质层，其中封装信号连接部分地覆盖RF无源元件相对于 集成电路的表面。 RF无源元件可以是电感器，变压器，电容器，晶体管或另一无源元件。 封装信号连接例如可以是导电球，导电凸块，导电垫或导电弹簧。 导电结构可以位于至少一个电介质层上，以提供对RF无源元件的屏蔽，并且可以包括多个导电元件或网状物。

公开(公告)号：US07633764B2

公开(公告)日：2009-12-15

申请号：US11115769

申请日：2005-04-27

申请人： Abhijit Mahajan ,  Ali Sarfaraz

发明人： Abhijit Mahajan ,  Ali Sarfaraz

IPC分类号： H05K7/00

CPC分类号： H05K1/181 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/10159 ,  H05K2201/10734 ,  Y02P70/611

摘要： Presented herein are ball grid array configurations for reducing path distances. In an exemplary embodiment, there is presented a memory system. The memory system comprises a printed circuit board, a memory controller, and a memory. The printed circuit board comprises a first layer and a second layer. The memory controller comprises a first plurality of pins connected to the first layer and a second plurality of pins connected to the second layer. The memory comprises a first plurality of pins connected to the first layer and a second plurality of pins connected to the second layer. The first layer comprises a plurality of connection paths connecting the first plurality of pins of the memory to the first plurality of pins of the memory controller. The second layer comprises a plurality of connection paths connecting the second plurality of pins of the memory to the second plurality of pins of the memory controller.

摘要翻译： 这里提出了用于减小路径距离的球栅阵列配置。 在示例性实施例中，呈现存储器系统。 存储器系统包括印刷电路板，存储器控制器和存储器。 印刷电路板包括第一层和第二层。 存储器控制器包括连接到第一层的第一多个引脚和连接到第二层的第二多个引脚。 存储器包括连接到第一层的第一多个引脚和连接到第二层的第二多个引脚。 第一层包括将存储器的第一多个引脚连接到存储器控制器的第一多个引脚的多个连接路径。 第二层包括将存储器的第二多个引脚连接到存储器控制器的第二多个引脚的多个连接路径。

公开(公告)号：US07932604B2

公开(公告)日：2011-04-26

申请号：US11150905

申请日：2005-06-13

申请人： Abhijit Mahajan ,  Ali Sarfaraz

发明人： Abhijit Mahajan ,  Ali Sarfaraz

IPC分类号： H01L23/48

CPC分类号： H05K1/181 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/10159 ,  H05K2201/10734 ,  Y02P70/611

摘要： Disclosed herein is a method and circuit arrangement for a multi-layer ball grid array configuration. In one embodiment, there is presented a board comprising a first surface, a second surface, and a plurality of vias. The second surface is connected to the first surface. The plurality of vias are positioned to form a substantially straight line on the first surface. The plurality of vias comprises a first via and a second via. The first via is adjacent to the second via. The first via emerges on the second surface on one side of the substantially straight line. The second via emerges on another side of the substantially straight line.

摘要翻译： 本文公开了一种用于多层球栅阵列配置的方法和电路装置。 在一个实施例中，呈现了包括第一表面，第二表面和多个通孔的板。 第二表面连接到第一表面。 多个通孔被定位成在第一表面上形成基本上直的线。 多个通孔包括第一通孔和第二通孔。 第一通孔与第二通孔相邻。 第一通孔出现在基本上直线的一侧的第二表面上。 第二通道出现在基本上直线的另一侧。

公开(公告)号：US20060245228A1

公开(公告)日：2006-11-02

申请号：US11115769

申请日：2005-04-27

申请人： Abhijit Mahajan ,  Ali Sarfaraz

发明人： Abhijit Mahajan ,  Ali Sarfaraz

IPC分类号： G11C5/02

CPC分类号： H05K1/181 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/10159 ,  H05K2201/10734 ,  Y02P70/611

摘要： Presented herein are ball grid array configurations for reducing path distances. In an exemplary embodiment, there is presented a memory system. The memory system comprises a printed circuit board, a memory controller, and a memory. The printed circuit board comprises a first layer and a second layer. The memory controller comprises a first plurality of pins connected to the first layer and a second plurality of pins connected to the second layer. The memory comprises a first plurality of pins connected to the first layer and a second plurality of pins connected to the second layer. The first layer comprises a plurality of connection paths connecting the first plurality of pins of the memory to the first plurality of pins of the memory controller. The second layer comprises a plurality of connection paths connecting the second plurality of pins of the memory to the second plurality of pins of the memory controller.

公开(公告)号：US20060273468A1

公开(公告)日：2006-12-07

申请号：US11150905

申请日：2005-06-13

申请人： Abhijit Mahajan ,  Ali Sarfaraz

发明人： Abhijit Mahajan ,  Ali Sarfaraz

IPC分类号： H01L23/48

CPC分类号： H05K1/181 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/10159 ,  H05K2201/10734 ,  Y02P70/611

摘要： Disclosed herein is a method and circuit arrangement for a multi-layer ball grid array configuration. In one embodiment, there is presented a board comprising a first surface, a second surface, and a plurality of vias. The second surface is connected to the first surface. The plurality of vias are positioned to form a substantially straight line on the first surface. The plurality of vias comprises a first via and a second via. The first via is adjacent to the second via. The first via emerges on the second surface on one side of the substantially straight line. The second via emerges on another side of the substantially straight line.

摘要翻译： 本文公开了一种用于多层球栅阵列配置的方法和电路装置。 在一个实施例中，呈现了包括第一表面，第二表面和多个通孔的板。 第二表面连接到第一表面。 多个通孔被定位成在第一表面上形成基本上直的线。 多个通孔包括第一通孔和第二通孔。 第一通孔与第二通孔相邻。 第一通孔出现在基本上直线的一侧的第二表面上。 第二通道出现在基本上直线的另一侧。