Abstract:
A driver circuit for driving a switching transistor includes a dead time calibration circuit and/or a quick start circuit. The dead time calibration circuit includes a delay comparator to compare a present delay between the low side switch turning off or the high side switch turning off and a voltage at a switch node between the high side switch and the low side switch to a past delay and a controller responsive to the comparison is configured to adjust the delay of an adjustable delay element coupled to a control terminal of a switching transistor. The quick start circuit includes a quick start signal generator having an adjustable delay element to generate a quick start signal having a pulse to turn on the switching transistor for a quick start interval, a quick start comparator configured to monitor the quick start signal, and a control circuit responsive to the comparison by the quick start comparator to adjust the delay of the delay element.
Abstract:
A driver circuit for driving a switching transistor includes a dead time calibration circuit and/or a quick start circuit. The dead time calibration circuit includes a delay comparator to compare a present delay between the low side switch turning off or the high side switch turning off and a voltage at a switch node between the high side switch and the low side switch to a past delay and a controller responsive to the comparison is configured to adjust the delay of an adjustable delay element coupled to a control terminal of a switching transistor. The quick start circuit includes a quick start signal generator having an adjustable delay element to generate a quick start signal having a pulse to turn on the switching transistor for a quick start interval, a quick start comparator configured to monitor the quick start signal, and a control circuit responsive to the comparison by the quick start comparator to adjust the delay of the delay element.
Abstract:
A driver circuit for driving a switching transistor having a control terminal responsive to a switching control signal includes a plurality of driver stages, each having a control input responsive to a respective driver control signal and an output coupled to the output of the other driver stages and to the control terminal of the switching transistor. At least one of the driver control signals has an on time that is delayed with respect to the other driver control signals. In an embodiment, at least two driver stages are on during a slew time interval.
Abstract:
A switching regulator control circuit comprises a first control circuit to control conduction of the switch according to a first mode of operation and having a regulation point and a second control circuit to control conduction of the switch according to a second mode of operation in response to a reference signal that is calibrated to have a predetermined relationship with respect to the regulation point of the first control circuit. In some embodiments, the reference signal is calibrated to be a predetermined amount greater than the regulation point of the first control circuit and may be calibrated during the first mode of operation or in response to a regulator start or restart event.
Abstract:
An integrated circuit an open pin detector includes a current source coupled to the pin, a comparator having a first input coupled to the pin, a second input responsive to a threshold voltage, and an output at which a comparator output signal is provided. A controller is responsive to the comparator output signal to provide an enable signal to the current source and an open pin signal indicative of an open pin condition at the pin. A method for detecting an open pin condition of a pin of an integrated circuit includes comparing the pin voltage to a first threshold voltage level, initiating open pin detection in response to the pin voltage falling below the first threshold voltage level, such as by providing a current to the pin, and indicating an open pin condition if the pin voltage rises to exceed a second threshold voltage level within a predetermined time interval. Also described is preventing the pin voltage from exceeding a predetermined voltage level during open pin detection.
Abstract:
A switching regulator control circuit comprises a first control circuit to control conduction of the switch according to a first mode of operation and having a regulation point and a second control circuit to control conduction of the switch according to a second mode of operation in response to a reference signal that is calibrated to have a predetermined relationship with respect to the regulation point of the first control circuit. In some embodiments, the reference signal is calibrated to be a predetermined amount greater than the regulation point of the first control circuit and may be calibrated during the first mode of operation or in response to a regulator start or restart event.
Abstract:
A switching voltage regulator with variable minimum off-time. The value of the minimum off-time may depend on the voltage across a bootstrap capacitor. The value of the minimum off-time defines a minimum time for a switch to be open and to allow the bootstrap capacitor to charge.
Abstract:
A switching voltage regulator with variable minimum off-time. The value of the minimum off-time may depend on the voltage across a bootstrap capacitor.
Abstract:
A switching regulator control circuit includes a circuit configured to generate a control signal to control conduction of the regulator switch in response to a reference signal that is ramped to control a rate of change of the regulated output of the regulator and the control signal is gated in response to a PWM signal.
Abstract:
As integrated circuit as open pin detector includes a current source coupled to the pin, a comparator having a first input coupled to the pin, a second input responsive to a threshold voltage, and an output at which a comparator output signal is provided. A controller is responsive to the comparator output signal to provide an enable signed, to the current source and an open pin signal indicative of an open pin condition at the pin. An open pin condition can be detected by comparing the pin voltage to a first threshold voltage level initiating open pin detection in response to the pin voltage falling below the first threshold voltage level, such as by providing a current to the pin, and indicating an open pin condition if the pin voltage rises to exceed a second threshold voltage level within a predetermined time interval. The pin voltage may be prevented from exceeding a predetermined voltage level during open pin detection.