公开(公告)号：US06180533B2

公开(公告)日：2001-01-30

申请号：US09545700

申请日：2000-04-07

申请人： Alok Jain ,  Michelle Siew Mooi Low ,  Gang Zou ,  David Mui ,  Dragan Podlesnik ,  Wei Liu

发明人： Alok Jain ,  Michelle Siew Mooi Low ,  Gang Zou ,  David Mui ,  Dragan Podlesnik ,  Wei Liu

IPC分类号： H01L2100

CPC分类号： H01L21/3065 ,  H01L21/3081 ,  H01L21/76232

摘要： The present disclosure includes a method of plasma etching a trench having rounded top corners in a silicon substrate. One embodiment includes the following general steps: a) providing a semiconductor structure comprising a hard masking layer, overlying a silicon substrate; b) plasma etching through said hard masking layer and any additional underlying layers overlying said silicon substrate using at least one plasma feed gas which does not provide polymer deposition on surfaces of said semiconductor structure during etching; where said plasma etching exposes a face of said silicon substrate; and c) plasma etching at least a first portion of a trench into said silicon substrate using reactive species generated from a feed gas comprising a source of fluorine, a source of carbon, a source of hydrogen, and a source of high energy species which provide physical bombardment of said silicon substrate. Top corner rounding is effected by deposition of a thin layer of polymer on a top corner of the trench during etching of the first portion of the trench, resulting in the formation of a rounded “shoulder” at the top corner of the trench. Typically a layer of silicon oxide overlies at least a portion of the silicon substrate surface. The method described provides excellent critical dimension control over the active area of a transistor produced using the method and reduces the need to remove polymer from substrate and reactor surfaces after etching of the silicon trench.

摘要翻译： 本公开内容包括等离子体蚀刻在硅衬底中具有圆形顶角的沟槽的方法。 一个实施例包括以下一般步骤：a）提供包括覆盖硅衬底的硬掩模层的半导体结构; b）使用至少一种在蚀刻期间不提供聚合物沉积在所述半导体结构的表面上的等离子体进料气体来等离子体蚀刻通过所述硬掩模层和覆盖所述硅衬底的任何附加的底层; 其中所述等离子体蚀刻暴露所述硅衬底的表面; 以及c）使用由包含氟源，碳源，氢源和高能量源的进料气体产生的反应性物质将沟槽的至少第一部分等离子体蚀刻到所述硅基板中，所述源提供 所述硅衬底的物理轰击。 通过在沟槽的第一部分的蚀刻期间在沟槽的顶角上沉积聚合物薄层来实现顶角圆角化，导致在沟槽的顶角形成圆形“肩部”。 通常，氧化硅层覆盖硅衬底表面的至少一部分。 所描述的方法提供了使用该方法制造的晶体管的有源面积的优异临界尺寸控制，并且减少了在蚀刻硅沟槽之后从衬底和反应器表面除去聚合物的需要。

公开(公告)号：US06235643B1

公开(公告)日：2001-05-22

申请号：US09371966

申请日：1999-08-10

申请人： David Mui ,  Dragan Podlesnik ,  Wei Liu ,  Gene Lee ,  Nam-Hun Kim ,  Jeff Chinn

发明人： David Mui ,  Dragan Podlesnik ,  Wei Liu ,  Gene Lee ,  Nam-Hun Kim ,  Jeff Chinn

IPC分类号： H01L2100

CPC分类号： H01L21/76232 ,  H01L21/3065 ,  H01L21/3081

摘要： The present invention provides straight forward methods for plasma etching a trench having rounded top corners, or rounded bottom corners, or both in a silicon substrate. A first method for creating a rounded top corner on the etched silicon trench comprises etching both an overlying silicon oxide layer and an upper portion of the silicon substrate during a “break-through” step which immediately precedes the step in which the silicon trench is etched. The plasma feed gas for the break-through step comprises carbon and fluorine. In this method, the photoresist layer used to pattern the etch stack is preferably not removed prior to the break-through etching step. Subsequent to the break-through step, a trench is etched to a desired depth in the silicon substrate using a different plasma feed gas composition. A second method for creating a rounded top corner on the etched silicon trench comprises formation of a built-up extension on the sidewall of an overlying patterned silicon nitride hard mask during etch (break-through) of a silicon oxide adhesion layer which lies between the hard mask and a silicone substrate. The built-up extension upon the silicon nitride sidewall acts as a sacrificial masking material during etch of the silicon trench, delaying etching of the silicon at the outer edges of the top of the trench. This permits completion of trench etching with delayed etching of the top corner of the trench and provides a more gentle rounding (increased radius) at the top corners of the trench. During the etching of the silicon trench to its final dimensions, it is desirable to round the bottom corners of the finished silicon trench. We have discovered that a more rounded bottom trench corner is obtained using a two-step silicon etch process where the second step of the process is carried out at a higher process chamber pressure than the first step.

摘要翻译： 本发明提供了用于在硅衬底中等离子体蚀刻具有圆形顶角或圆形底角或两者的沟槽的直接方法。 用于在蚀刻的硅沟槽上形成圆角顶角的第一种方法包括：在“穿透”步骤​​期间蚀刻覆盖硅氧化物层和硅衬底的上部两者之间，其中硅裂纹之前的步骤 。 用于穿透步骤的等离子体进料气体包括碳和氟。 在该方法中，用于图案化蚀刻叠层的光致抗蚀剂层优选在穿透蚀刻步骤之前不被去除。 在突破步骤之后，使用不同的等离子体进料气体组合物将沟槽蚀刻到硅衬底中的所需深度。 用于在蚀刻的硅沟槽上产生圆角顶角的第二种方法包括在位于第二层之间的氧化硅粘合层的蚀刻（穿透）期间在覆盖的图案化氮化硅硬掩模的侧壁上形成积层延伸。 硬面罩和硅胶基材。 在硅氮化物侧壁上的累积延伸在硅沟槽的蚀刻期间用作牺牲掩模材料，延迟在沟槽顶部的外边缘处的硅的蚀刻。 这允许通过延迟蚀刻沟槽的顶角完成沟槽蚀刻，并且在沟槽的顶角提供更温和的圆化（增加的半径）。 在将硅沟槽蚀刻到其最终尺寸期间，期望圆形完成的硅沟槽的底角。 我们已经发现，使用两步硅蚀刻工艺获得更圆的底部沟槽角，其中该工艺的第二步骤在比第一步高的处理室压力下进行。

公开(公告)号：US20060091108A1

公开(公告)日：2006-05-04

申请号：US11263780

申请日：2005-10-31

申请人： David Mui ,  Wei Liu ,  Hiroki Sasano

发明人： David Mui ,  Wei Liu ,  Hiroki Sasano

IPC分类号： G01L21/30 ,  B44C1/22 ,  C23F1/00

CPC分类号： G03F7/70625 ,  H01L21/67207 ,  H01L21/67253 ,  H01L22/20

摘要： A method for controlling etch processes during fabrication of semiconductor devices comprises tests and measurements performed on non-product and product substrates to define an N-parameter CD control graph that is used to calculate a process time for trimming a patterned mask to a pre-determined width. An apparatus for performing such a method.

公开(公告)号：US20070202706A1

公开(公告)日：2007-08-30

申请号：US11743882

申请日：2007-05-03

申请人： David Mui ,  Wei Liu

发明人： David Mui ,  Wei Liu

IPC分类号： H01L21/461 ,  H01L21/302

CPC分类号： H01L21/32137

摘要： A method and apparatus for etching material layers with high uniformity of a lateral etch rate across a substrate using a gas mixture that includes a passivation gas. The passivation gas is provided to a peripheral region of the substrate to passivate sidewalls of the structures being etched.

公开(公告)号：US07250373B2

公开(公告)日：2007-07-31

申请号：US10927807

申请日：2004-08-27

申请人： David Mui ,  Wei Liu

发明人： David Mui ,  Wei Liu

IPC分类号： H01L21/302

CPC分类号： H01L21/32137

摘要： A method and apparatus for etching material layers with high uniformity of a lateral etch rate across a substrate using a gas mixture that includes a passivation gas. The passivation gas is provided to a peripheral region of the substrate to passivate sidewalls of the structures being etched.

摘要翻译： 一种用于使用包括钝化气体的气体混合物在衬底上蚀刻具有高均匀度横向蚀刻速率的材料层的方法和装置。 钝化气体被提供到衬底的周边区域以钝化被蚀刻的结构的侧壁。

公开(公告)号：US06911399B2

公开(公告)日：2005-06-28

申请号：US10665934

申请日：2003-09-19

申请人： Wei Liu ,  David Mui

发明人： Wei Liu ,  David Mui

IPC分类号： H01L21/3065 ,  G03F7/40 ,  H01L21/027 ,  H01L21/311 ,  H01L21/302

CPC分类号： H01L21/31138 ,  G03F7/40 ,  H01L21/0274

摘要： A method for trimming photoresist features on a semiconductor substrate in a processing system. The method utilizes a process gas mixture comprising a hydrocarbon gas, an oxygen gas and an inert gas. The critical dimension (CD) microloading of the dense and the isolated regions can be eliminated and the photoresist trimming rate can also be reduced to enable better critical dimension (CD) control.

公开(公告)号：US06703315B2

公开(公告)日：2004-03-09

申请号：US10165894

申请日：2002-06-10

申请人： Wei Liu ,  David Mui

发明人： Wei Liu ,  David Mui

IPC分类号： H01L21302

CPC分类号： H01L27/10861 ,  H01L21/76232

摘要： A method of forming a shallow trench within a trench capacitor structure. This method can be used, for example, in the construction of a DRAM device. The method comprises: (1) providing a trench capacitor structure comprising (a) a silicon substrate having an upper and a lower surface; (b) first and second trenches extending from the upper surface into the silicon substrate; (c) first and second oxide regions lining at least portions of the first and second trenches; and (d) first and second polysilicon regions at least partially filling the oxide lined first and second trenches; and (2) forming a shallow trench from an upper surface of the structure, the shallow trench having a substantially flat trench bottom that forms an interface with portions of the silicon substrate, the first oxide region, the second oxide region, the first polysilicon region and the second polysilicon region, the shallow trench being formed by a process comprising (a) a first plasma etching step having an oxide:silicon:polysilicon selectivity of 1:1:1, more preferably >1.3:1:1.

摘要翻译： 一种在沟槽电容器结构内形成浅沟槽的方法。 该方法可以用于例如DRAM器件的构造。 该方法包括：（1）提供一种沟槽电容器结构，其包括（a）具有上表面和下表面的硅衬底; （b）从上表面延伸到硅衬底中的第一和第二沟槽; （c）在第一和第二沟槽的至少一部分内衬的第一和第二氧化物区域; 和（d）至少部分地填充氧化物衬里的第一和第二沟槽的第一和第二多晶硅区域; 和（2）从结构的上表面形成浅沟槽，浅沟槽具有基本平坦的沟槽底部，其与硅衬底，第一氧化物区域，第二氧化物区域，第一多晶硅区域的部分形成界面 和第二多晶硅区域，所述浅沟槽通过包括（a）第一等离子体蚀刻步骤形成的工艺，所述第一等离子体蚀刻步骤具有氧化物：硅：多晶硅选择性<1：1：1，和（b）第二等离子体蚀刻步骤，其具有氧化物 硅：多晶硅选择性> 1：1，更优选> 1.3:1:1。

公开(公告)号：US20070295455A1

公开(公告)日：2007-12-27

申请号：US11831357

申请日：2007-07-31

申请人： David Mui ,  Wei Liu

发明人： David Mui ,  Wei Liu

IPC分类号： H01L21/3065

CPC分类号： H01L21/32137

摘要： A method and apparatus for etching material layers with high uniformity of a lateral etch rate across a substrate using a gas mixture that includes a passivation gas. The passivation gas is provided to a peripheral region of the substrate to passivate sidewalls of the structures being etched.

摘要翻译： 一种用于使用包括钝化气体的气体混合物在衬底上蚀刻具有高均匀度横向蚀刻速率的材料层的方法和装置。 钝化气体被提供到衬底的周边区域以钝化被蚀刻的结构的侧壁。

公开(公告)号：US20050085090A1

公开(公告)日：2005-04-21

申请号：US10690318

申请日：2003-10-21

申请人： David Mui ,  Wei Liu ,  Hiroki Sasano

发明人： David Mui ,  Wei Liu ,  Hiroki Sasano

IPC分类号： H01L21/3065 ,  G03F7/20 ,  H01L21/00 ,  H01L21/02 ,  H01L21/302 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/461

CPC分类号： H01L21/02071 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139

摘要： Embodiments of the invention generally relate to a method for etching in a processing platform (e.g. a cluster tool) wherein robust pre-etch and post-etch data may be obtained in-situ. The method includes the steps of obtaining pre-etched critical dimension (CD) measurements of a feature on a substrate, etching the feature; treating the etched substrate to reduce and/or remove sidewall polymers deposited on the feature during etching, and obtaining post-etched CD measurements. The CD measurements may be utilized to adjust the etch process to improved the accuracy and repeatability of device fabrication.

摘要翻译： 本发明的实施例通常涉及在处理平台（例如，集群工具）中蚀刻的方法，其中可以原位获得鲁棒的预蚀刻和蚀刻后数据。 该方法包括以下步骤：获得衬底上特征的预蚀刻临界尺寸（CD）测量值，蚀刻该特征; 处理蚀刻的衬底以在蚀刻期间减少和/或去除沉积在特征上的侧壁聚合物，并获得后蚀刻的CD测量。 可以使用CD测量来调整蚀刻工艺以提高器件制造的精度和可重复性。

公开(公告)号：US20050064719A1

公开(公告)日：2005-03-24

申请号：US10665934

申请日：2003-09-19

申请人： Wei Liu ,  David Mui

发明人： Wei Liu ,  David Mui

IPC分类号： H01L21/3065 ,  G03F7/40 ,  H01L21/027 ,  H01L21/311 ,  H01L21/302 ,  H01L21/00 ,  H01L21/461

CPC分类号： H01L21/31138 ,  G03F7/40 ,  H01L21/0274

摘要： A method for trimming photoresist features on a semiconductor substrate in a processing system. The method utilizes a process gas mixture comprising a hydrocarbon gas, an oxygen gas and an inert gas. The critical dimension (CD) microloading of the dense and the isolated regions can be eliminated and the photoresist trimming rate can also be reduced to enable better critical dimension (CD) control.

摘要翻译： 一种用于在处理系统中修整半导体衬底上的光致抗蚀剂特征的方法。 该方法利用包括烃气体，氧气和惰性气体的工艺气体混合物。 可以消除致密和孤立区域的临界尺寸（CD）微载荷，并且还可以减少光刻胶修整速率，以实现更好的临界尺寸（CD）控制。