Very Low Power Microcontroller System
    1.
    发明申请

    公开(公告)号:US20190079575A1

    公开(公告)日:2019-03-14

    申请号:US16013767

    申请日:2018-06-20

    Abstract: A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

    Very Low Power Microcontroller System
    2.
    发明申请

    公开(公告)号:US20190079574A1

    公开(公告)日:2019-03-14

    申请号:US16005315

    申请日:2018-06-11

    Abstract: A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

    Very Low Power Microcontroller System
    9.
    发明申请

    公开(公告)号:US20190079573A1

    公开(公告)日:2019-03-14

    申请号:US15933153

    申请日:2018-03-22

    Abstract: A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

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