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    Very Low Power Microcontroller System
    2.
    发明申请
    Very Low Power Microcontroller System 审中-公开

    公开(公告)号：US20190079573A1

    公开(公告)日：2019-03-14

    申请号：US15933153

    申请日：2018-03-22

    Applicant: Ambiq Micro, Inc.

    Inventor： Scott McLean Hanson ,  Daniel Martin Cermak ,  Eric Jonathan Deal ,  Stephen James Sheafor ,  Donovan Scott Popps ,  Mark A. Baur

    IPC: G06F1/32

    Abstract: A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

    ON-DEMAND ACTIVATION OF MEMORY PATH DURING SLEEP OR ACTIVE MODES
    3.
    发明公开
    ON-DEMAND ACTIVATION OF MEMORY PATH DURING SLEEP OR ACTIVE MODES 审中-公开

    公开(公告)号：US20240354012A1

    公开(公告)日：2024-10-24

    申请号：US18760849

    申请日：2024-07-01

    Applicant: Ambiq Micro, Inc.

    Inventor： Daniel Martin Cermak ,  Scott McLean Hanson ,  Yousof Mortazavi ,  Ramakanth Kondagunturi

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0626 ,  G06F3/0655 ,  G06F3/0673

    Abstract: A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.

    On-demand activation of memory path during sleep or active modes
    7.
    发明授权
    On-demand activation of memory path during sleep or active modes 有权

    公开(公告)号：US12050789B2

    公开(公告)日：2024-07-30

    申请号：US17981149

    申请日：2022-11-04

    Applicant: Ambiq Micro, Inc.

    Inventor： Daniel Martin Cermak ,  Scott McLean Hanson ,  Yousof Mortazavi ,  Ramakanth Kondagunturi

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0626 ,  G06F3/0655 ,  G06F3/0673

    Abstract: A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.

    Enhanced peripheral processing system to optimize power consumption
    9.
    发明授权
    Enhanced peripheral processing system to optimize power consumption 有权

    公开(公告)号：US11620246B1

    公开(公告)日：2023-04-04

    申请号：US17752554

    申请日：2022-05-24

    Applicant: Ambiq Micro, Inc.

    Inventor： Stephen James Sheafor ,  Daniel Martin Cermak ,  Roger Serwy ,  Marc Miller

    IPC: G06F13/28 ,  G06F13/16 ,  G06F1/3296

    Abstract: A microcontroller system that includes a central processing unit (CPU), a first system memory, a first peripheral module, and a DMA controller is disclosed. The DMA controller includes a DMA processor, a DMA memory, and a DMA interconnect. The DMA memory stores information associated with the DMA processor. The DMA processor receives a command from the CPU or a signal from a peripheral processor of the first peripheral module that a first data transfer is requested. The DMA processor receives first data from the first system memory or the first peripheral module. The DMA processor, based at least in part on the information stored in the DMA memory, transmits the first data to the first peripheral module or the first system memory, thereby sparing the CPU from managing the transferring of the first data.

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