Automated well test validation
    1.
    发明授权

    公开(公告)号:US10480305B2

    公开(公告)日:2019-11-19

    申请号:US15229658

    申请日:2016-08-05

    IPC分类号: E21B44/00

    摘要: A diagnostic apparatus configured to communicate with a well test system comprising a plurality of wells in a field, comprising a receiving component configured to receive a well test data from the well test system, a transmitting component configured to transmit an abnormal well test signal indication, at least one processor configured to communicate with the transmitting component and the receiving component, and a memory coupled to the at least one processor, wherein the memory comprises instructions that when executed by the at least one processor cause the diagnostic apparatus to compare the well test data to one or more well test descriptors stored in memory, correlate the well test data to an abnormal well test result selected based at least in part on the comparison with the one or more well test descriptors stored in the memory, and instruct the transmitting component to transmit an abnormal well test signal indication to a recipient.

    Automated Well Test Validation
    2.
    发明申请
    Automated Well Test Validation 审中-公开
    自动井测试验证

    公开(公告)号:US20170058659A1

    公开(公告)日:2017-03-02

    申请号:US15229658

    申请日:2016-08-05

    IPC分类号: E21B47/00 E21B34/00 E21B43/34

    CPC分类号: E21B44/00

    摘要: A diagnostic apparatus configured to communicate with a well test system comprising a plurality of wells in a field, comprising a receiving component configured to receive a well test data from the well test system, a transmitting component configured to transmit an abnormal well test signal indication, at least one processor configured to communicate with the transmitting component and the receiving component, and a memory coupled to the at least one processor, wherein the memory comprises instructions that when executed by the at least one processor cause the diagnostic apparatus to compare the well test data to one or more well test descriptors stored in memory, correlate the well test data to an abnormal well test result selected based at least in part on the comparison with the one or more well test descriptors stored in the memory, and instruct the transmitting component to transmit an abnormal well test signal indication to a recipient.

    摘要翻译: 一种诊断装置,被配置为与包括现场的多个井的井测试系统进行通信,所述井测试系统包括被配置为从所述井测试系统接收井测试数据的接收组件,被配置为发送异常井测试信号指示的发射组件, 至少一个处理器,被配置为与所述发射部件和所述接收部件进行通信;以及存储器,其耦合到所述至少一个处理器,其中,所述存储器包括当所述至少一个处理器执行时使所述诊断装置比较所述测试 数据存储到存储器中的一个或多个井测试描述符,将井测试数据与至少部分地基于与存储在存储器中的一个或多个井测试描述符进行比较而选择的异常井测试结果相关联,并且指示发射组件 以将异常井测试信号指示传送给接收者。

    Determining Interwell Communication
    3.
    发明申请
    Determining Interwell Communication 审中-公开
    确定Interwell通信

    公开(公告)号:US20130110485A1

    公开(公告)日:2013-05-02

    申请号:US13646363

    申请日:2012-10-05

    IPC分类号: G06G7/48

    CPC分类号: G01V99/005

    摘要: There is provided a system and method for determining interwell communication in a hydrocarbon-producing field that has a plurality of wells. An exemplary method comprises determining communication relationships for the plurality of wells using a multivariate dynamic joint analysis algorithm based on data representing properties of each of the plurality of wells. The multivariate dynamic joint analysis algorithm may employ a self-response of each of the plurality of wells and an interwell response between combinations of the plurality of wells. Data representative of the communication relationships is provided.

    摘要翻译: 提供了一种用于确定具有多个井的烃生产领域中的井间通信的系统和方法。 示例性方法包括使用基于表示多个井中的每个井的属性的数据的多变量动态联合分析算法确定多个井的通信关系。 多变量动态联合分析算法可以采用多个井中的每一个的自身响应和多个井的组合之间的井间响应。 提供代表通信关系的数据。

    System and method for detecting non-contact repellency of a compound candidate from Drosophila

    公开(公告)号:US10948398B1

    公开(公告)日:2021-03-16

    申请号:US15986097

    申请日:2018-05-22

    申请人: Peng Xu

    发明人: Peng Xu

    摘要: An assay system for a repellent includes transparent tubing having end chambers; a central testing area positioned between the end chambers; small openings between the central testing area and end chambers; absorbent material positioned adjacent to the openings and being soaked in either a control substance or a repellent; and fruit flies are introduced into the central testing area and allowed to migrate through the openings and into either end chamber.

    Training acoustic models using distributed computing techniques
    8.
    发明授权
    Training acoustic models using distributed computing techniques 有权
    使用分布式计算技术训练声学模型

    公开(公告)号:US08959014B2

    公开(公告)日:2015-02-17

    申请号:US13539225

    申请日:2012-06-29

    摘要: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for training acoustic models. Speech data and data identifying a transcription for the speech data are received. A phonetic representation for the transcription is accessed. Training sequences are identified for a particular phone in the phonetic representation. Each of the training sequences includes a different set of contextual phones surrounding the particular phone. A partitioning key is identified based on a sequence of phones that occurs in each of the training sequences. A processing module to which the identified partitioning key is assigned is selected. Data identifying the training sequences and a portion of the speech data are transmitted to the selected processing module.

    摘要翻译: 方法,系统和装置,包括在计算机存储介质上编码的用于训练声学模型的计算机程序。 接收用于识别语音数据的转录的语音数据和数据。 访问转录的语音表示。 在语音表示中为特定电话识别训练序列。 每个训练序列包括围绕特定电话的不同的上下文电话组。 基于在每个训练序列中出现的电话序列来识别分区密钥。 选择分配了所识别的分区键的处理模块。 识别训练序列和语音数据的一部分的数据被发送到所选择的处理模块。

    DELAY CIRCUIT AND ASSOCIATED METHOD
    10.
    发明申请
    DELAY CIRCUIT AND ASSOCIATED METHOD 有权
    延时电路及相关方法

    公开(公告)号:US20130257502A1

    公开(公告)日:2013-10-03

    申请号:US13431595

    申请日:2012-03-27

    申请人: Yan Dong Peng Xu

    发明人: Yan Dong Peng Xu

    IPC分类号: H03H11/26

    摘要: The embodiments of the present invention disclose a delay circuit. The delay circuit comprises an inverter, a load capacitor, and a first voltage clamping module, wherein the first voltage clamping module generates a voltage drop configured to prolong the propagation delay time of the delay circuit as the power supply voltage decreases. The power supply dependent delay circuit may have a much larger propagation delay time at low power supply voltage than it at high power supply voltage at the rising-edge or falling-edge of an input signal.

    摘要翻译: 本发明的实施例公开了延迟电路。 所述延迟电路包括反相器,负载电容器和第一电压钳位模块,其中所述第一电压钳位模块产生电压降,所述电压降配置为当所述电源电压降低时延长所述延迟电路的传播延迟时间。 电源相关延迟电路在低电源电压下的输入信号上升沿或下降沿处的高电源电压可能具有大得多的传播延迟时间。