公开(公告)号：US20240282848A1

公开(公告)日：2024-08-22

申请号：US18560066

申请日：2021-12-08

Applicant: Analog Devices, Inc.

Inventor： James G. Fiorenza ,  Christopher John Day ,  Guanghai Ding ,  Daniel Piedra

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/40 ,  H03K17/687

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/407 ,  H03K17/687

Abstract: A semiconductor device including a transistor having a threshold voltage for switching the transistor from a first conductive state to a second conductive state. The transistor includes a first region formed by a first compound semiconductor material and a second region formed by a second compound semiconductor material, where the second region overlying the first region and forming a two-dimensional electron gas (2DEG) at a junction with the first region. The transistor further includes a buried field plate disposed proximate to the first region so that the 2DEG is interposed between the buried field plate and the second region. The semiconductor device further includes a control circuit configured to adjust the threshold voltage of the transistor by providing a bias voltage to the buried field plate responsive to an input signal received at the transistor.

公开(公告)号：US20240405105A1

公开(公告)日：2024-12-05

申请号：US18204095

申请日：2023-05-31

Applicant: Analog Devices, Inc.

Inventor： F. Jacob Steigerwald ,  James G. Fiorenza ,  Guanghai Ding ,  Susan L. Feindt ,  Pengfei Wu ,  Clifford Alan King

IPC: H01L29/737 ,  H01L21/84 ,  H01L27/12 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66

Abstract: Techniques of integrating lateral HBT devices into a silicon on insulator (SOI) CMOS process. Similar approaches could also be applied to Fin Field-Effect Transistors (FinFETs). A first technique makes use of a CMOS replacement gate process that is typically associated with a partially depleted SOI (PDSOI) or fully depleted SOI (FDSOI) process. A second technique is independent of the CMOS process. Both techniques can accommodate silicon germanium (SiGe) and/or III-V materials, include a self-aligned base contact, and can be used to construct both NPN and PNP transistors with varied peak fT and breakdown voltages.

公开(公告)号：US20240213354A1

公开(公告)日：2024-06-27

申请号：US18069824

申请日：2022-12-21

Applicant: Analog Devices, Inc.

Inventor： James G. Fiorenza ,  Guanghai Ding ,  Daniel Piedra

IPC: H01L29/66 ,  H01L21/04 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L21/046 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/7786

Abstract: Techniques to increase the number of current paths (or “channels”) in a GaN transistor, without increasing the device area, thereby decreasing the on-resistance. In addition, this disclosure describes techniques to utilize back-side field management to improve the device's performance. For example, the techniques can include using p-type implantation into the substrate, e.g., silicon carbide (SiC), as a field management tool to form a superjunction device, thereby increasing the effective field and reducing the on-resistance multiplied by the output charge (Qoss).