公开(公告)号：US09800262B1

公开(公告)日：2017-10-24

申请号：US15258910

申请日：2016-09-07

Applicant: Analog Devices Global

Inventor： Roberto Sergio Matteo Maurino ,  Sanjay Rajasekhar ,  Pasquale Delizia ,  Colin G. Lyden ,  Gabriel Banarie

IPC: H03M3/00 ,  H03M1/08

CPC classification number: H03M3/464 ,  H03M1/08 ,  H03M3/34 ,  H03M3/452

Abstract: A sigma delta analog-to-digital converter (ADC) circuit comprises a capacitive gain amplifier circuit having a first input to receive an input voltage and a second input; a loop filter circuit connected to an output of the capacitive gain amplifier circuit; a sub-ADC circuit including an output and an input connected to an output of the loop filter circuit; and a digital-to-analog (DAC) circuit including a DAC input connected to the output of the sub-ADC circuit, and a DAC output connected to the second input of the capacitive gain amplifier.

公开(公告)号：US20170255221A1

公开(公告)日：2017-09-07

申请号：US15464056

申请日：2017-03-20

Applicant: Analog Devices Global

Inventor： Stefan Marinca ,  Gabriel Banarie

IPC: G05F3/30 ,  G05F3/16

CPC classification number: G05F3/30 ,  G05F3/16

Abstract: The present disclosure relates to a method and apparatus for generating a voltage reference. More particularly the present disclosure relates to a methodology and circuitry configured to provide an output signal that combines a proportional to absolute temperature component with a complimentary to absolute temperature component to generate a stable output which is not temperature dependent.

公开(公告)号：US09806552B2

公开(公告)日：2017-10-31

申请号：US15169981

申请日：2016-06-01

Applicant: Analog Devices Global

Inventor： Paraic Brannick ,  Colin G. Lyden ,  Damien J. McCartney ,  Gabriel Banarie

IPC: H03M1/60 ,  H02J7/00 ,  G04F10/00 ,  H03M1/20 ,  H03M1/50 ,  H02J7/34

CPC classification number: H02J7/007 ,  G04F10/005 ,  H02J7/345 ,  H03M1/201 ,  H03M1/50 ,  H03M1/52 ,  H03M1/60

Abstract: A charge rebalancing integration circuit can help keep an output node of a front-end integration circuit within a specified range, e.g., without requiring resetting of the integration capacitor. The process of monitoring and rebalancing the integration circuit can operate on a much shorter time base than the integration time period, which can allow for multiple charge balancing charge transfer events during the integration time period, and sampling of the integration capacitor once per integration time period, such as at the end of that integration time period. Information about the charge rebalancing can be used to adjust subsequent discrete-time signal processing, such as digitized values of the samples. Improved dynamic range and noise performance is possible. Computed tomography (CT) imaging and other use cases are described, including those with variable integration periods.

公开(公告)号：US10236905B1

公开(公告)日：2019-03-19

申请号：US15901177

申请日：2018-02-21

Applicant: Analog Devices Global Unlimited Company

Inventor： Andreas Callanan ,  Adrian Sherry ,  Gabriel Banarie ,  Colin G. Lyden

IPC: H03M1/06 ,  H03M3/00 ,  H03H17/02

Abstract: Techniques to increase a data throughput rate of a filter circuit by preloading selectable memory circuits of the filter circuit with reference data, sampling input data at an input of the filter circuit, combining the sampled input data with the preloaded reference data, and generating a filter output based on the combined sampled input data and preloaded reference data.

公开(公告)号：US20170237268A1

公开(公告)日：2017-08-17

申请号：US15169981

申请日：2016-06-01

Applicant: Analog Devices Global

Inventor： Paraic Brannick ,  Colin G. Lyden ,  Damien J. McCartney ,  Gabriel Banarie

IPC: H02J7/00 ,  H03M1/20

CPC classification number: H02J7/007 ,  G04F10/005 ,  H02J7/345 ,  H03M1/201 ,  H03M1/50 ,  H03M1/52 ,  H03M1/60

Abstract: A charge rebalancing integration circuit can help keep an output node of a front-end integration circuit within a specified range, e.g., without requiring resetting of the integration capacitor. The process of monitoring and rebalancing the integration circuit can operate on a much shorter time base than the integration time period, which can allow for multiple charge balancing charge transfer events during the integration time period, and sampling of the integration capacitor once per integration time period, such as at the end of that integration time period. Information about the charge rebalancing can be used to adjust subsequent discrete-time signal processing, such as digitized values of the samples. Improved dynamic range and noise performance is possible. Computed tomography (CT) imaging and other use cases are described, including those with variable integration periods.

公开(公告)号：US09600014B2

公开(公告)日：2017-03-21

申请号：US14272061

申请日：2014-05-07

Applicant: ANALOG DEVICES GLOBAL

Inventor： Stefan Marinca ,  Gabriel Banarie

IPC: G05F3/30 ,  G05F3/16

CPC classification number: G05F3/30 ,  G05F3/16

Abstract: The present disclosure relates to a method and apparatus for generating a voltage reference. More particularly the present disclosure relates to a methodology and circuitry configured to provide an output signal that combines a proportional to absolute temperature component with a complimentary to absolute temperature component to generate a stable output which is not temperature dependent.