利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

34 条记录 (耗时 0.024 秒)

    System and method for accurate negative bias temperature instability characterization
    1.
    发明申请
    System and method for accurate negative bias temperature instability characterization 有权
    准确的负偏压温度不稳定性表征的系统和方法

    公开(公告)号：US20060049842A1

    公开(公告)日：2006-03-09

    申请号：US10935375

    申请日：2004-09-07

    申请人： Anand Krishnan ,  Srikanth Krishnan ,  Vijay Reddy ,  Cathy Chancellor

    发明人： Anand Krishnan ,  Srikanth Krishnan ,  Vijay Reddy ,  Cathy Chancellor

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2621

    摘要： Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.

    摘要翻译： 提供了用于表征晶体管的负温度偏置不稳定性的方法和系统。 在测试期间，晶体管的漏极端子保持偏置电压。 在测试期间，在晶体管的栅极端子处保持应力电压，使得与偏置电压同时施加应力电压。 在应力周期期间以周期性间隔测量晶体管的至少一个特性，以确定由应力电压引起的直到终止事件发生的至少一个特性的劣化。

    System and method for accurate negative bias temperature instability characterization
    4.
    发明授权
    System and method for accurate negative bias temperature instability characterization 有权
    准确的负偏压温度不稳定性表征的系统和方法

    公开(公告)号：US07212023B2

    公开(公告)日：2007-05-01

    申请号：US10935375

    申请日：2004-09-07

    申请人： Anand T. Krishnan ,  Srikanth Krishnan ,  Vijay Reddy ,  Cathy Chancellor

    发明人： Anand T. Krishnan ,  Srikanth Krishnan ,  Vijay Reddy ,  Cathy Chancellor

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2621

    摘要： Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.

    摘要翻译： 提供了用于表征晶体管的负温度偏置不稳定性的方法和系统。 在测试期间，晶体管的漏极端子保持偏置电压。 在测试期间，在晶体管的栅极端子处保持应力电压，使得与偏置电压同时施加应力电压。 在应力周期期间以周期性间隔测量晶体管的至少一个特性，以确定由应力电压引起的直到终止事件发生的至少一个特性的劣化。

    Semiconductor antenna proximity lines
    5.
    发明申请
    Semiconductor antenna proximity lines 有权
    半导体天线接近线

    公开(公告)号：US20050133826A1

    公开(公告)日：2005-06-23

    申请号：US11042669

    申请日：2005-01-25

    申请人： Anand Krishnan ,  Srikanth Krishnan

    发明人： Anand Krishnan ,  Srikanth Krishnan

    IPC分类号： H01L23/52 ,  H01L27/10 ,  H01L29/73

    CPC分类号： H01L23/52 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An embodiment of the invention is an integrated circuit 2 having antenna proximity lines 3 coupled to the semiconductor substrate 5. Another embodiment of the invention is a method of manufacturing an integrated circuit 2 having antenna proximity lines 3 coupled to the semiconductor substrate 5.

    摘要翻译： 本发明的实施例是具有耦合到半导体衬底5的天线接近线3的集成电路2。 本发明的另一个实施例是一种制造具有耦合到半导体衬底5的天线接近线3的集成电路2的方法。

    Method and system for reducing charge damage in silicon-on-insulator technology
    6.
    发明申请
    Method and system for reducing charge damage in silicon-on-insulator technology 有权

    公开(公告)号：US20070264804A1

    公开(公告)日：2007-11-15

    申请号：US11782523

    申请日：2007-07-24

    申请人： James Gallia ,  Srikanth Krishnan ,  Anand Krishnan

    发明人： James Gallia ,  Srikanth Krishnan ,  Anand Krishnan

    IPC分类号： H01L21/20

    CPC分类号： H01L27/1203

    摘要： According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.

    INTEGRATED CIRCUIT MODELING, DESIGN, AND FABRICATION BASED ON DEGRADATION MECHANISMS
    9.
    发明申请
    INTEGRATED CIRCUIT MODELING, DESIGN, AND FABRICATION BASED ON DEGRADATION MECHANISMS 有权
    基于降解机制的集成电路建模，设计和制造

    公开(公告)号：US20100038683A1

    公开(公告)日：2010-02-18

    申请号：US12192850

    申请日：2008-08-15

    申请人： Ajit Shanware ,  Srikanth Krishnan

    发明人： Ajit Shanware ,  Srikanth Krishnan

    IPC分类号： H01L29/94 ,  G06F17/00 ,  H01L21/66

    CPC分类号： H01L27/092 ,  H01L27/0207

    摘要： An integrated circuit (IC) includes at least a first complementary MOS (CMOS) circuit, the first CMOS circuit comprising one or more first n-channel MOS (NMOS) transistors and one or more first p-channel MOS (PMOS) transistors, where the first NMOS transistors and the first PMOS transistors are arranged in the first CMOS circuit to drive at least a first common node of the first CMOS circuit. An average of the effective gate channel lengths of the first NMOS transistors (first NMOS average length) is at least 2% greater than an average of the effective gate channel lengths of the first PMOS transistors (first PMOS average length).

    摘要翻译： 集成电路（IC）至少包括第一互补MOS（CMOS）电路，第一CMOS电路包括一个或多个第一n沟道MOS（NMOS）晶体管和一个或多个第一p沟道MOS（PMOS）晶体管，其中 第一NMOS晶体管和第一PMOS晶体管布置在第一CMOS电路中以驱动第一CMOS电路的至少第一公共节点。 第一NMOS晶体管的有效栅极沟道长度的平均值（第一NMOS平均长度）比第一PMOS晶体管的有效栅极沟道长度的平均值（第一PMOS平均长度）至少大2％。

    Bistable fuse by amorphization of polysilicon
    10.
    发明授权
    Bistable fuse by amorphization of polysilicon 有权
    双稳态保险丝通过多晶硅非晶化

    公开(公告)号：US6117745A

    公开(公告)日：2000-09-12

    申请号：US148260

    申请日：1998-09-04

    申请人： Srikanth Krishnan

    发明人： Srikanth Krishnan

    IPC分类号： H01L23/525 ,  H01L21/20

    CPC分类号： H01L23/5256 ,  H01L2924/0002

    摘要： An embodiment of the instant invention is a method of substantially isolating an electrical device over a semiconductor substrate from a structure which collects charge, the method comprising the steps of: forming an insulating layer (layer 304) on the substrate; forming a conductive layer (layer 306) on the insulating layer; incorporating at least one element (element 310) into portions of the conductive layer so as to render that portion the conductive layer more resistive; and wherein the portion of the conductive layer which has been rendered more resistive (region 312) is rendered conductive after one or more charging events by subjecting the portion of the conductive layer to an elevated temperature. Preferably, the element is comprised of an element selected from the group comprised of: As, P, N, Ar, Si, H, B, Ge, C, Sb, F, Cl, O, any noble element, and any combination thereof and their isotopes. The structure which collects charge is, preferably, a conductive structure (structure 11) which collects charge during plasma processing.

    摘要翻译： 本发明的一个实施例是一种从收集电荷的结构基本上隔离半导体衬底上的电子器件的方法，该方法包括以下步骤：在衬底上形成绝缘层（层304）; 在绝缘层上形成导电层（层306）; 将至少一个元件（元件310）结合到导电层的部分中，以使该部分导电层更具阻性; 并且其中通过使导电层的一部分经历升高的温度，在一个或多个充电事件之后，已经变得更加电阻（区域312）的导电层的部分变得导电。 优选地，元素由选自As，P，N，Ar，Si，H，B，Ge，C，Sb，F，Cl，O，任何贵金属及其任何组合的元素组成 及其同位素。 收集电荷的结构优选地是在等离子体处理期间收集电荷的导电结构（结构11）。