公开(公告)号：US20050133826A1

公开(公告)日：2005-06-23

申请号：US11042669

申请日：2005-01-25

申请人： Anand Krishnan ,  Srikanth Krishnan

发明人： Anand Krishnan ,  Srikanth Krishnan

IPC分类号： H01L23/52 ,  H01L27/10 ,  H01L29/73

CPC分类号： H01L23/52 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of the invention is an integrated circuit 2 having antenna proximity lines 3 coupled to the semiconductor substrate 5. Another embodiment of the invention is a method of manufacturing an integrated circuit 2 having antenna proximity lines 3 coupled to the semiconductor substrate 5.

摘要翻译： 本发明的实施例是具有耦合到半导体衬底5的天线接近线3的集成电路2。 本发明的另一个实施例是一种制造具有耦合到半导体衬底5的天线接近线3的集成电路2的方法。

公开(公告)号：US20060049842A1

公开(公告)日：2006-03-09

申请号：US10935375

申请日：2004-09-07

申请人： Anand Krishnan ,  Srikanth Krishnan ,  Vijay Reddy ,  Cathy Chancellor

发明人： Anand Krishnan ,  Srikanth Krishnan ,  Vijay Reddy ,  Cathy Chancellor

IPC分类号： G01R31/26

CPC分类号： G01R31/2621

摘要： Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.

摘要翻译： 提供了用于表征晶体管的负温度偏置不稳定性的方法和系统。 在测试期间，晶体管的漏极端子保持偏置电压。 在测试期间，在晶体管的栅极端子处保持应力电压，使得与偏置电压同时施加应力电压。 在应力周期期间以周期性间隔测量晶体管的至少一个特性，以确定由应力电压引起的直到终止事件发生的至少一个特性的劣化。

公开(公告)号：US20070264804A1

公开(公告)日：2007-11-15

申请号：US11782523

申请日：2007-07-24

申请人： James Gallia ,  Srikanth Krishnan ,  Anand Krishnan

发明人： James Gallia ,  Srikanth Krishnan ,  Anand Krishnan

IPC分类号： H01L21/20

CPC分类号： H01L27/1203

摘要： According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.

公开(公告)号：US20060076971A1

公开(公告)日：2006-04-13

申请号：US11290077

申请日：2005-11-30

申请人： Anand Krishnan ,  Srikanth Krishnan ,  Vijay Reddy ,  Cathy Chancellor

发明人： Anand Krishnan ,  Srikanth Krishnan ,  Vijay Reddy ,  Cathy Chancellor

IPC分类号： G01R31/26

CPC分类号： G01R31/2621

摘要： Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.

公开(公告)号：US06770937B1

公开(公告)日：2004-08-03

申请号：US10409560

申请日：2003-04-08

申请人： Anand Krishnan ,  Srikanth Krishnan

发明人： Anand Krishnan ,  Srikanth Krishnan

IPC分类号： H01L2362

CPC分类号： H01L24/02 ,  H01L23/552 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/14 ,  H01L2924/30105

摘要： A semiconductor device (200) that includes a semiconductor substrate (210), semiconductor features (230, 235, 240, 260) located thereover and an insulating photoconductive layer (270) coupling the semiconductor features (230, 235, 240, 260). The photoconductive layer (270) is configured to provide conductivity between the semiconductor features (230, 235, 240, 260) in a presence of a plasma.

摘要翻译： 一种半导体器件（200），包括半导体衬底（210），位于其上的半导体特征（230,235,240,260）和耦合所述半导体特征（230,235,240,260）的绝缘光电导层（270）。 光电导层（270）被配置为在存在等离子体的情况下在半导体特征（230,235,240,260）之间提供导电性。

公开(公告)号：US06582977B1

公开(公告)日：2003-06-24

申请号：US10230703

申请日：2002-08-29

申请人： John Rodriguez ,  Anand Krishnan

发明人： John Rodriguez ,  Anand Krishnan

IPC分类号： G01R3126

CPC分类号： H01L22/34

摘要： Methods are disclosed for determining charging related to one or more semiconductor processing steps. A wafer having a substantially unpolarized ferroelectric capacitor formed therein is exposed to a processing operation. After processing, the ferroelectric capacitor is measured to determine the extent to which the processing operation polarized the ferroelectric capacitor, and a process related charging value is determined according to the ferroelectric capacitor polarization.

摘要翻译： 公开了用于确定与一个或多个半导体处理步骤有关的充电的方法。 在其中形成有基本上非偏振的铁电电容器的晶片暴露于处理操作。 在处理之后，测量铁电电容器以确定对铁电电容器进行极化处理操作的程度，并且根据铁电电容器极化确定处理相关充电值。

公开(公告)号：US07682988B2

公开(公告)日：2010-03-23

申请号：US10930230

申请日：2004-08-31

申请人： Husam N. Alshareef ,  Rajesh Khamankar ,  Ajith Varghese ,  Cathy A. Chancellor ,  Anand Krishnan ,  Malcolm J. Bevan

发明人： Husam N. Alshareef ,  Rajesh Khamankar ,  Ajith Varghese ,  Cathy A. Chancellor ,  Anand Krishnan ,  Malcolm J. Bevan

IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L21/8234

CPC分类号： H01L21/02326 ,  H01L21/0214 ,  H01L21/02337 ,  H01L21/265 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/823857 ,  H01L29/518 ,  H01L29/7833

摘要： A method of reducing threshold voltage shift of a MOSFET transistor resulting after temperature and voltage stress, and an integrated circuit device fabricated according to the method. The method includes the steps of forming a nitrided dielectric layer on a semiconductor substrate, and subjecting the nitrided dielectric layer to an anneal at low pressure.

摘要翻译： 一种降低在温度和电压应力之后导致的MOSFET晶体管的阈值电压偏移的方法，以及根据该方法制造的集成电路器件。 该方法包括以下步骤：在半导体衬底上形成氮化介电层，并将氮化介电层在低压下进行退火。

公开(公告)号：US20050208776A1

公开(公告)日：2005-09-22

申请号：US11083912

申请日：2005-03-18

申请人： Anand Krishnan ,  Srinivasan Chakravarthi ,  Haowen Bu

发明人： Anand Krishnan ,  Srinivasan Chakravarthi ,  Haowen Bu

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/318 ,  H01L21/469 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/7842 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02274 ,  H01L21/28211 ,  H01L21/31662 ,  H01L21/3185 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/7833

摘要： The present invention provides, in one aspect, a method of fabricating a gate oxide layer on a microelectronics substrate. This embodiment comprises forming a stress inducing pattern on a backside of a microelectronics wafer and growing a gate oxide layer on a front side of the microelectronics wafer in the presence of a tensile stress caused by the stress inducing pattern.

摘要翻译： 本发明在一个方面提供了一种在微电子衬底上制造栅氧化层的方法。 该实施例包括在微电子晶片的背面上形成应力诱导图案，并且在由应力诱导图案引起的拉伸应力的存在下，在微电子晶片的正面上生长栅极氧化物层。

公开(公告)号：US20180299449A1

公开(公告)日：2018-10-18

申请号：US15481213

申请日：2017-04-06

申请人： Madhavan Radhakrishna Pillai ,  Mani Shankar Babu ,  Praveen Kunjan Sobhan ,  Anand Krishnan ,  Mahendra Seervi ,  Rakesh Sathish Nair

发明人： Madhavan Radhakrishna Pillai ,  Mani Shankar Babu ,  Praveen Kunjan Sobhan ,  Anand Krishnan ,  Mahendra Seervi ,  Rakesh Sathish Nair

IPC分类号： G01N33/574

CPC分类号： G01N33/57426 ,  C07D401/12 ,  C07D405/14 ,  G01N33/558 ,  G01N2333/82 ,  G01N2800/52

摘要： This document provides methods and materials for identifying individuals with protein tyrosine kinase associated disorders for responsiveness to a kinase inhibitor (e.g., imatinib or nilotinib). For example, methods and materials for using a chemi-immunochromatographic lateral flow strip for detection of BCR-ABL and drug resistance are provided.

公开(公告)号：US20070210421A1

公开(公告)日：2007-09-13

申请号：US11374635

申请日：2006-03-13

申请人： Haowen Bu ,  Anand Krishnan ,  Ting Tsui ,  William Dostalik ,  Rajesh Khamankar

发明人： Haowen Bu ,  Anand Krishnan ,  Ting Tsui ,  William Dostalik ,  Rajesh Khamankar

IPC分类号： H01L23/58 ,  H01L21/469

CPC分类号： H01L21/02167 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/268 ,  H01L21/3105 ,  H01L21/3148 ,  H01L21/318 ,  H01L21/324 ,  H01L21/76829 ,  H01L21/823828 ,  H01L21/823871 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides, one aspect, a method of fabricating a semiconductor device. In one aspect, the method includes forming a carbide layer over a gate electrode and depositing a pre-metal dielectric layer over the carbide layer. The method provides a significant reduction in NBTI drift.

摘要翻译： 本发明一方面提供一种制造半导体器件的方法。 一方面，该方法包括在栅电极上形成碳化物层，并在碳化物层上沉积预金属电介质层。 该方法显着降低了NBTI漂移。