Semiconductor antenna proximity lines
    1.
    发明申请
    Semiconductor antenna proximity lines 有权
    半导体天线接近线

    公开(公告)号:US20050133826A1

    公开(公告)日:2005-06-23

    申请号:US11042669

    申请日:2005-01-25

    IPC分类号: H01L23/52 H01L27/10 H01L29/73

    摘要: An embodiment of the invention is an integrated circuit 2 having antenna proximity lines 3 coupled to the semiconductor substrate 5. Another embodiment of the invention is a method of manufacturing an integrated circuit 2 having antenna proximity lines 3 coupled to the semiconductor substrate 5.

    摘要翻译: 本发明的实施例是具有耦合到半导体衬底5的天线接近线3的集成电路2。 本发明的另一个实施例是一种制造具有耦合到半导体衬底5的天线接近线3的集成电路2的方法。

    Methods for determining charging in semiconductor processing
    2.
    发明授权
    Methods for determining charging in semiconductor processing 有权
    用于确定半导体处理中的充电的方法

    公开(公告)号:US06582977B1

    公开(公告)日:2003-06-24

    申请号:US10230703

    申请日:2002-08-29

    IPC分类号: G01R3126

    CPC分类号: H01L22/34

    摘要: Methods are disclosed for determining charging related to one or more semiconductor processing steps. A wafer having a substantially unpolarized ferroelectric capacitor formed therein is exposed to a processing operation. After processing, the ferroelectric capacitor is measured to determine the extent to which the processing operation polarized the ferroelectric capacitor, and a process related charging value is determined according to the ferroelectric capacitor polarization.

    摘要翻译: 公开了用于确定与一个或多个半导体处理步骤有关的充电的方法。 在其中形成有基本上非偏振的铁电电容器的晶片暴露于处理操作。 在处理之后,测量铁电电容器以确定对铁电电容器进行极化处理操作的程度,并且根据铁电电容器极化确定处理相关充电值。

    System and method for accurate negative bias temperature instability characterization
    5.
    发明申请
    System and method for accurate negative bias temperature instability characterization 有权
    准确的负偏压温度不稳定性表征的系统和方法

    公开(公告)号:US20060049842A1

    公开(公告)日:2006-03-09

    申请号:US10935375

    申请日:2004-09-07

    IPC分类号: G01R31/26

    CPC分类号: G01R31/2621

    摘要: Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.

    摘要翻译: 提供了用于表征晶体管的负温度偏置不稳定性的方法和系统。 在测试期间,晶体管的漏极端子保持偏置电压。 在测试期间,在晶体管的栅极端子处保持应力电压,使得与偏置电压同时施加应力电压。 在应力周期期间以周期性间隔测量晶体管的至少一个特性,以确定由应力电压引起的直到终止事件发生的至少一个特性的劣化。

    Method and system for the reduction of off-state current in field effect
transistors
    6.
    发明授权
    Method and system for the reduction of off-state current in field effect transistors 失效
    在场效应晶体管中减少截止电流的方法和系统

    公开(公告)号:US5945866A

    公开(公告)日:1999-08-31

    申请号:US807611

    申请日:1997-02-27

    IPC分类号: G09G3/36

    摘要: A method for reducing the field dependence of an off-state current flow condition in a field-effect transistor having a source electrode, a drain electrode and a gate electrode, includes the steps of: applying a far off-state bias between the drain electrode and the gate electrode to drive a conduction channel in the field effect transistor into a far off-state; and applying a far off-state bias between the source electrode and the gate electrode to again drive the conduction channel into a far off-state; wherein both applying steps cause application of the far off-state bias for a sufficient time to reduce gate voltage dependency of off-state current flow in the conduction channel during a period when an off-state potential is applied to the gate electrode.

    摘要翻译: 一种用于降低具有源电极,漏电极和栅电极的场效应晶体管中的截止电流流动状态的场依赖性的方法包括以下步骤:在漏极之间施加远离状态偏置 以及栅电极,将场效应晶体管的导通通道驱动为远离状态; 以及在所述源电极和所述栅电极之间施加远离状态偏置以再次将所述导通通道驱动到远离状态; 其中两个施加步骤使得在关闭状态电位施加到栅极电极的时段期间施加远离状态偏压足够的时间以减小导通通道中截止态电流的栅极电压依赖性。