公开(公告)号：US20050047037A1

公开(公告)日：2005-03-03

申请号：US10874125

申请日：2004-06-22

申请人： Andrej Litwin ,  Ola Pettersson

发明人： Andrej Litwin ,  Ola Pettersson

IPC分类号： H01L20060101 ,  H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0266 ,  H01L27/0288

摘要： A device for ESD protection of a high frequency circuit (1) of a semiconductor device comprises first (3) and second (4) p-type and first (6) and second (5) n-type JFET's, wherein the first p-type JFET (3) is connected with its gate to a high voltage source, its source to an input/output pad (2) of the semiconductor device, and its drain to the source of the first n-type JFET (6), the second p-type JFET (4) is connected with its gate to the high voltage source, its source to the drain of the second n-type JFET (5), and its drain to an input/output terminal of the circuit (1), the first n-type JFET transistor (6) is connected with its gate to ground (GND), and its drain to the input/output terminal, and the second n-type JFET transistor (5) is connected with its gate to ground (GND), and its source to the input/output pad (2).

摘要翻译： 用于半导体器件的高频电路（1）的ESD保护的器件包括第一（3）和第二（4）p型和第一（6）和第二（5）n型JFET，其中， 类型JFET（3）与其栅极连接到高电压源，其源极到半导体器件的输入/输出焊盘（2），并且其漏极到第一n型JFET（6）的源极， 第二p型JFET（4）与其栅极连接到高压源，其源极连接到第二n型JFET（5）的漏极，并且其漏极连接到电路（1）的输入/输出端子， ，第一n型JFET晶体管（6）与其栅极接地（GND）连接，其漏极连接到输入/输出端子，第二n型JFET晶体管（5）与其栅极连接 （GND），其源极到输入/输出焊盘（2）。

公开(公告)号：US07019382B2

公开(公告)日：2006-03-28

申请号：US10791389

申请日：2004-03-02

申请人： Andrej Litwin ,  Ola Pettersson

发明人： Andrej Litwin ,  Ola Pettersson

IPC分类号： H01L29/00

CPC分类号： H01L27/0251

摘要： To protect a high-frequency integrated circuit (1) against higher voltages than normal operating voltages on an input/output terminal connected to a bonding pad (2), a semiconductor varistor (3) having low and essentially constant resistance for said normal operating voltages and higher resistance for said higher voltages is integrated between the bonding pad (2) and the input/output terminal together with the integrated circuit (1).

摘要翻译： 为了保护高频集成电路（1）免受连接到焊盘（2）的输入/输出端子上的正常工作电压的较高电压，对于所述正常工作电压具有低且基本上恒定的电阻的半导体压敏电阻（3） 并且所述较高电压的较高电阻与集成电路（1）一起集成在焊盘（2）和输入/输出端子之间。

公开(公告)号：US20070075784A1

公开(公告)日：2007-04-05

申请号：US11496133

申请日：2006-07-31

申请人： Ola Pettersson ,  Andrej Litwin

发明人： Ola Pettersson ,  Andrej Litwin

IPC分类号： H03F1/22

CPC分类号： H03F1/223 ,  H03F3/45188 ,  H03F2203/45464

摘要： The present invention relates to a cascode radio frequency power amplifier, including at least two cascaded MOS transistors formed in a mutual substrate, where the bulk nodes of the transistors are isolated from each other and connected to the respective source of each transistor. The present invention also teaches that the drain of the topmost transistor is connected to the power supply through an inductive load, and that the gate of each upper transistor is equipped with a self-biasing circuit connected at least between the drain and the gate of the respective upper transistor.

摘要翻译： 共射型射频功率放大器技术领域本发明涉及一种共源共射型射频功率放大器，其包括形成在相互衬底中的至少两个级联MOS晶体管，其中晶体管的体节点彼此隔离并连接到每个晶体管的相应源极。 本发明还教导了最顶层晶体管的漏极通过电感负载连接到电源，并且每个上部晶体管的栅极配备有至少在漏极和栅极之间连接的自偏置电路 各自的上部晶体管。

公开(公告)号：US07227730B2

公开(公告)日：2007-06-05

申请号：US11141986

申请日：2005-05-31

申请人： Andrej Litwin ,  Ola Pettersson

发明人： Andrej Litwin ,  Ola Pettersson

IPC分类号： H02H9/00 ,  H02H3/22 ,  H02H1/00 ,  H02H1/04 ,  H02H9/06 ,  H01C7/12

CPC分类号： H01L27/0288

摘要： A device for ESD (electrostatic discharge) protection of a circuit of a semiconductor device comprises a field effect transistor based varistor with gate, source and drain regions, wherein one of the source and drain regions is connected to an input/output pad of the semiconductor device, and the other one of the source and drain regions is connected to an input/output terminal of the circuit. A biasing circuit is connected to the gate region of the varistor to create an accumulation region below the gate of the varistor at normal operating voltages of said semiconductor device. The semiconductor device is preferably an integrated device on a single substrate.

摘要翻译： 用于半导体器件的电路的ESD（静电放电）保护的装置包括具有栅极，源极和漏极区域的场效应晶体管基压敏电阻，其中源区和漏极区之一连接到半导体的输入/输出焊盘 器件，源极和漏极区域中的另一个连接到电路的输入/输出端子。 偏置电路连接到压敏电阻的栅极区域，以在所述半导体器件的正常工作电压下产生在压敏电阻栅极下方的累积区域。 半导体器件优选地是在单个衬底上的集成器件。

公开(公告)号：US07164567B2

公开(公告)日：2007-01-16

申请号：US10874125

申请日：2004-06-22

申请人： Andrej Litwin ,  Ola Pettersson

发明人： Andrej Litwin ,  Ola Pettersson

IPC分类号： H02H3/22

CPC分类号： H01L27/0266 ,  H01L27/0288

摘要： A device for ESD protection of a high frequency circuit (1) of a semiconductor device comprises first (3) and second (4) p-type and first (6) and second (5) n-type JFET's, wherein the first p-type JFET (3) is connected with its gate to a high voltage source, its source to an input/output pad (2) of the semiconductor device, and its drain to the source of the first n-type JFET (6), the second p-type JFET (4) is connected with its gate to the high voltage source, its source to the drain of the second n-type JFET (5), and its drain to an input/output terminal of the circuit (1), the first n-type JFET transistor (6) is connected with its gate to ground (GND), and its drain to the input/output terminal, and the second n-type JFET transistor (5) is connected with its gate to ground (GND), and its source to the input/output pad (2).

摘要翻译： 用于半导体器件的高频电路（1）的ESD保护的器件包括第一（3）和第二（4）p型和第一（6）和第二（5）n型JFET，其中， 类型JFET（3）与其栅极连接到高电压源，其源极到半导体器件的输入/输出焊盘（2），并且其漏极到第一n型JFET（6）的源极， 第二p型JFET（4）与其栅极连接到高压源，其源极连接到第二n型JFET（5）的漏极，并且其漏极连接到电路（1）的输入/输出端子， ，第一n型JFET晶体管（6）与其栅极接地（GND）连接，其漏极连接到输入/输出端子，第二n型JFET晶体管（5）与其栅极连接 （GND），其源极到输入/输出焊盘（2）。

公开(公告)号：US20060018066A1

公开(公告)日：2006-01-26

申请号：US11141986

申请日：2005-05-31

申请人： Andrej Litwin ,  Ola Pettersson

发明人： Andrej Litwin ,  Ola Pettersson

IPC分类号： H02H9/00

CPC分类号： H01L27/0288

摘要： A device for ESD (electrostatic discharge) protection of a circuit of a semiconductor device comprises a field effect transistor based varistor with gate, source and drain regions, wherein one of the source and drain regions is connected to an input/output pad of the semiconductor device, and the other one of the source and drain regions is connected to an input/output terminal of the circuit. A biasing circuit is connected to the gate region of the varistor to create an accumulation region below the gate of the varistor at normal operating voltages of said semiconductor device. The semiconductor device is preferably an integrated device on a single substrate.

摘要翻译： 用于半导体器件的电路的ESD（静电放电）保护的装置包括具有栅极，源极和漏极区域的场效应晶体管基压敏电阻，其中源区和漏极区之一连接到半导体的输入/输出焊盘 器件，源极和漏极区域中的另一个连接到电路的输入/输出端子。 偏置电路连接到压敏电阻的栅极区域，以在所述半导体器件的正常工作电压下产生在压敏电阻栅极下方的累积区域。 半导体器件优选地是在单个衬底上的集成器件。

公开(公告)号：US06507047B2

公开(公告)日：2003-01-14

申请号：US09858902

申请日：2001-05-17

申请人： Andrej Litwin

发明人： Andrej Litwin

IPC分类号： H01L310312

CPC分类号： H01L29/0692 ,  H01L29/1608 ,  H01L29/812

摘要： A field effect transistor is made on a chip comprising a SiC-substrate. The transistor includes a plurality of densely stacked parallel transistor cells occupying totally a rectangular area. Each transistor cell has parallel strip-shaped regions forming the electrodes and active areas of the cell and each inner cell shares its drain and sources electrodes with neighbouring cells. In order to give a good power dissipation allowing an electrical high power of the transistor, the rectangular area has a very elongated shape and specifically it should have a width not larger than substantially 50 &mgr;m. In the rectangular area all the transistor cells have their strip-shaped regions located in parallel to short sides of the rectangular area and are generally very short considering the length of the rectangular area. Thus specifically also each cell has a length not larger than substantially 50 &mgr;m. The distances from the long sides of the rectangular area to the edges of the chip should be at least 50% and preferably 60% of the thickness of the chip to allow a good thermal flow out of the active rectangular area. A plurality of such very elongated active areas can be located on a single chip.

摘要翻译： 在包括SiC衬底的芯片上形成场效应晶体管。 晶体管包括占据整个矩形区域的多个密集堆叠的平行晶体管单元。 每个晶体管单元具有形成电极的平行条形区域和电池的有效区域，并且每个内部电池与相邻电池共享其漏极和源极。 为了提供允许晶体管的高功率的良好的功率耗散，矩形区域具有非常细长的形状，具体地，其宽度应不大于基本上为50μm。 在矩形区域中，所有晶体管单元的条形区域与矩形区域的短边平行，并且考虑到矩形区域的长度通常非常短。 因此，具体地，每个电池具有不大于基本上50μm的长度。 从矩形区域的长边到芯片的边缘的距离应至少为芯片厚度的50％，优选地为60％，以允许良好的热流出有源矩形区域。 多个这样非常细长的有源区域可以位于单个芯片上。

公开(公告)号：US20060003727A1

公开(公告)日：2006-01-05

申请号：US11156982

申请日：2005-06-20

申请人： Andrej Litwin ,  Ganesh Kathiresan

发明人： Andrej Litwin ,  Ganesh Kathiresan

IPC分类号： H04B1/18 ,  H04B1/26

CPC分类号： H03D7/1441 ,  H03D7/1458 ,  H03D2200/0084 ,  H03D2200/009

摘要： An RF front-end receiver comprises a low noise amplifier and a local oscillator driver, which are connected to respective input ports of a mixer which comprises a first and second transistor with gates coupled to one output terminal, a third and fourth transistor with gates coupled to the other output terminal, a fifth and sixth transistor with gates coupled to respective output terminal of the local oscillator driver, the sources of the first and third transistors coupled to the drain of the fifth transistor, the sources of the second and fourth transistor coupled to the drain of the sixth transistor, the sources of the fifth and sixth transistor coupled to ground, the drains of the first and fourth transistor coupled to one output terminal of a mixer output port, and the drains of the second and third transistor coupled to the other output terminal of the mixer output port.

摘要翻译： RF前端接收机包括低噪声放大器和本地振荡器驱动器，其连接到混频器的相应输入端口，混频器包括具有耦合到一个输出端子的栅极的第一和第二晶体管，栅极耦合的第三和第四晶体管 到另一个输出端，具有耦合到本地振荡器驱动器的相应输出端的栅极的第五和第六晶体管，耦合到第五晶体管的漏极的第一和第三晶体管的源极，第二和第四晶体管的源极耦合 到第六晶体管的漏极，第五和第六晶体管的源极耦合到地，第一和第四晶体管的漏极耦合到混频器输出端口的一个输出端，并且第二和第三晶体管的漏极耦合到 混频器输出端口的另一个输出端子。

公开(公告)号：US20050112822A1

公开(公告)日：2005-05-26

申请号：US10947801

申请日：2004-09-23

申请人： Andrej Litwin

发明人： Andrej Litwin

IPC分类号： H01L20060101 ,  H01L21/265 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/0653 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A method in the fabrication of an integrated high frequency circuit including a DMOS transistor device comprises the steps of providing a substrate, etching a trench in a region defined for an extended drain for the DMOS transistor, and doping a region below the trench and a region at a side of the trench to a first doping type by means of ion implantation in the etched open trench through a mask, wherein the ion implantation is effectuated in a direction, which is inclined at an angle to the normal of the surface of the substrate, to thereby create a partly lateral and partly vertical current path in the extended drain. The method comprises further the steps of filling the trench with an insulating material to form a shallow trench isolation region, and forming a gate, a channel region, a source, and a drain for the DMOS transistor.

摘要翻译： 制造包括DMOS晶体管器件的集成高频电路的方法包括以下步骤：提供衬底，在限定用于DMOS晶体管的扩展漏极的区域中蚀刻沟槽，以及掺杂沟槽下方的区域和区域 在通过掩模在蚀刻的开放沟槽中借助于离子注入到第一掺杂类型的沟槽的一侧，其中离子注入沿着与衬底的表面的法线成一角度倾斜的方向实现 ，从而在延伸的漏极中产生部分横向和部分垂直的电流路径。 该方法还包括以下步骤：用绝缘材料填充沟槽以形成浅沟槽隔离区，以及为DMOS晶体管形成栅极，沟道区，源极和漏极。

公开(公告)号：US6100770A

公开(公告)日：2000-08-08

申请号：US150231

申请日：1998-09-09

申请人： Andrej Litwin ,  Sven Erik Mattisson

发明人： Andrej Litwin ,  Sven Erik Mattisson

IPC分类号： H01L20060101 ,  H01L29/93 ,  H01L29/94 ,  H03B5/12 ,  H03K3/354

CPC分类号： H03K3/354 ,  H01L29/94 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1253 ,  H03B2200/0098

摘要： An electrical device having a voltage dependent capacitance is provided comprising a first region of a semiconductor material, and a second region and a third region of a semiconductor material formed in the first region, the second and third regions being separated by a separation region, and an electrically insulating layer formed on the first region at least at a region corresponding to the separation region, and a substantially conductive element formed on the insulating layer at least at a region corresponding to the separation region such that the insulating layer electrically insulates the substantially conductive element from the first, second and third regions, and a first electrode connected to the substantially conductive element, and a second electrode and third electrode are connected to the second and third regions. A method of manufacturing the device is also disclosed.

摘要翻译： 提供具有电压相关电容的电气装置，其包括半导体材料的第一区域和形成在第一区域中的第二区域和半导体材料的第三区域，第二和第三区域被分离区域分开，以及 至少在对应于分离区域的区域上形成在第一区域上的电绝缘层，以及至少在对应于分离区域的区域上形成在绝缘层上的基本上导电的元件，使得绝缘层将绝缘层电绝缘 元件和与第一，第二和第三区域连接的第一电极，第二电极和第三电极连接到第二和第三区域。 还公开了一种制造该器件的方法。