公开(公告)号：US08614123B2

公开(公告)日：2013-12-24

申请号：US13305131

申请日：2011-11-28

申请人： Andy Wei ,  Peter Baars ,  Erik Geiss

发明人： Andy Wei ,  Peter Baars ,  Erik Geiss

IPC分类号： H01L21/8238

CPC分类号： H01L21/28079 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： Disclosed herein are various methods of forming a semiconductor device using sacrificial gate electrodes and sacrificial self-aligned contacts. In one example, the method includes forming two spaced-apart sacrificial gate electrodes comprised of a first material, forming a sacrificial contact structure comprised of a second material, wherein the second material is selectively etchable with respect to said first material, and performing an etching process on the two spaced-apart sacrificial gate electrodes and the sacrificial contact structure to selectively remove the two spaced-apart sacrificial gate electrode structures selectively relative to the sacrificial contact structure.

摘要翻译： 本文公开了使用牺牲栅电极和牺牲自对准触点形成半导体器件的各种方法。 在一个示例中，该方法包括形成由第一材料构成的两个间隔开的牺牲栅电极，形成包括第二材料的牺牲接触结构，其中第二材料相对于所述第一材料可选择性地蚀刻，并且执行蚀刻 在两个间隔开的牺牲栅电极和牺牲接触结构之间进行选择性地相对于牺牲接触结构选择性地去除两个间隔开的牺牲栅极电极结构。

公开(公告)号：US20130137257A1

公开(公告)日：2013-05-30

申请号：US13305131

申请日：2011-11-28

申请人： Andy Wei ,  Peter Baars ,  Erik Geiss

发明人： Andy Wei ,  Peter Baars ,  Erik Geiss

IPC分类号： H01L21/28

CPC分类号： H01L21/28079 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： Disclosed herein are various methods of forming a semiconductor device using sacrificial gate electrodes and sacrificial self-aligned contacts. In one example, the method includes forming two spaced-apart sacrificial gate electrodes comprised of a first material, forming a sacrificial contact structure comprised of a second material, wherein the second material is selectively etchable with respect to said first material, and performing an etching process on the two spaced-apart sacrificial gate electrodes and the sacrificial contact structure to selectively remove the two spaced-apart sacrificial gate electrode structures selectively relative to the sacrificial contact structure.

摘要翻译： 本文公开了使用牺牲栅电极和牺牲自对准触点形成半导体器件的各种方法。 在一个示例中，该方法包括形成由第一材料构成的两个间隔开的牺牲栅电极，形成包括第二材料的牺牲接触结构，其中第二材料相对于所述第一材料可选择性地蚀刻，并且执行蚀刻 在两个间隔开的牺牲栅电极和牺牲接触结构之间进行选择性地相对于牺牲接触结构选择性地去除两个间隔开的牺牲栅极电极结构。

公开(公告)号：US08927407B2

公开(公告)日：2015-01-06

申请号：US13354739

申请日：2012-01-20

申请人： Peter Baars ,  Andy Wei ,  Erik Geiss ,  Martin Mazur

发明人： Peter Baars ,  Andy Wei ,  Erik Geiss ,  Martin Mazur

IPC分类号： H01L21/28

CPC分类号： H01L21/76897 ,  H01L29/66545

摘要： Disclosed herein is a method of forming self-aligned contacts for a semiconductor device. In one example, the method includes forming a plurality of spaced-apart sacrificial gate electrodes above a semiconducting substrate, wherein each of the gate electrodes has a gate cap layer positioned on the gate electrode, and performing at least one etching process to define a self-aligned contact opening between the plurality of spaced-apart sacrificial gate electrodes. The method further includes removing the gate cap layers to thereby expose an upper surface of each of the sacrificial gate electrodes, depositing at least one layer of conductive material in said self-aligned contact opening and removing portions of the at least one layer of conductive material that are positioned outside of the self-aligned contact opening to thereby define at least a portion of a self-aligned contact positioned in the self-aligned contact opening.

摘要翻译： 本文公开了一种形成用于半导体器件的自对准接触件的方法。 在一个示例中，该方法包括在半导体衬底之上形成多个间隔开的牺牲栅电极，其中每个栅电极具有位于栅电极上的栅极帽层，并执行至少一个蚀刻工艺以限定自身 在多个间隔开的牺牲栅电极之间的对准接触开口。 该方法还包括去除栅极盖层，从而暴露每个牺牲栅电极的上表面，在所述自对准接触开口中沉积至少一层导电材料，并去除至少一层导电材料的部分 其定位在自对准接触开口的外侧，从而限定位于自对准接触开口中的自对准接触件的至少一部分。

公开(公告)号：US20130189833A1

公开(公告)日：2013-07-25

申请号：US13354739

申请日：2012-01-20

申请人： Peter Baars ,  Andy Wei ,  Erik Geiss ,  Martin Mazur

发明人： Peter Baars ,  Andy Wei ,  Erik Geiss ,  Martin Mazur

IPC分类号： H01L21/28

CPC分类号： H01L21/76897 ,  H01L29/66545

摘要： Disclosed herein is a method of forming self-aligned contacts for a semiconductor device. In one example, the method includes forming a plurality of spaced-apart sacrificial gate electrodes above a semiconducting substrate, wherein each of the gate electrodes has a gate cap layer positioned on the gate electrode, and performing at least one etching process to define a self-aligned contact opening between the plurality of spaced-apart sacrificial gate electrodes. The method further includes removing the gate cap layers to thereby expose an upper surface of each of the sacrificial gate electrodes, depositing at least one layer of conductive material in said self-aligned contact opening and removing portions of the at least one layer of conductive material that are positioned outside of the self-aligned contact opening to thereby define at least a portion of a self-aligned contact positioned in the self-aligned contact opening.

摘要翻译： 本文公开了一种形成用于半导体器件的自对准接触件的方法。 在一个示例中，该方法包括在半导体衬底之上形成多个间隔开的牺牲栅电极，其中每个栅电极具有位于栅电极上的栅极帽层，并执行至少一个蚀刻工艺以限定自身 在多个间隔开的牺牲栅电极之间的对准接触开口。 该方法还包括去除栅极盖层，从而暴露每个牺牲栅电极的上表面，在所述自对准接触开口中沉积至少一层导电材料，并去除至少一层导电材料的部分 其定位在自对准接触开口的外侧，从而限定位于自对准接触开口中的自对准接触件的至少一部分。

公开(公告)号：US08835245B2

公开(公告)日：2014-09-16

申请号：US13372604

申请日：2012-02-14

申请人： Peter Baars ,  Till Schloesser ,  Frank Jakubowski ,  Andy Wei ,  Richard Carter ,  Matthias Schaller

发明人： Peter Baars ,  Till Schloesser ,  Frank Jakubowski ,  Andy Wei ,  Richard Carter ,  Matthias Schaller

IPC分类号： H01L21/8234 ,  H01L21/768 ,  H01L21/285 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823475 ,  H01L21/28518 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/66636 ,  H01L29/7848

摘要： When forming sophisticated semiconductor devices, a replacement gate approach may be applied in combination with a self-aligned contact regime by forming the self-aligned contacts prior to replacing the placeholder material of the gate electrode structures.

摘要翻译： 当形成复杂的半导体器件时，可以在替换栅电极结构的占位符材料之前形成自对准触点，将替代栅极方法与自对准的接触方式结合使用。

公开(公告)号：US08647952B2

公开(公告)日：2014-02-11

申请号：US12974037

申请日：2010-12-21

申请人： Peter Baars ,  Richard Carter ,  Andy Wei

发明人： Peter Baars ,  Richard Carter ,  Andy Wei

IPC分类号： H01L21/336

CPC分类号： H01L27/092 ,  H01L21/28512 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/28 ,  H01L23/485 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7847 ,  H01L2924/0002 ,  H01L2924/00

摘要： Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein the pitch between adjacent gate electrodes is aggressively scaled, and wherein self-aligning contact elements may be utilized to avoid the high electrical resistance levels commonly associated with narrow contact elements formed using typically available photolithography techniques. One illustrative embodiment includes forming first and second gate electrode structures above a semiconductor substrate, then forming a first layer of a first dielectric material adjacent to or in contact with the sidewalls of each of the first and second gate electrode structures. The illustrative method further includes a step of forming a second layer of a second dielectric material on the first layer, followed by forming a third layer of a third dielectric material on the second layer, wherein forming the third layer further comprises forming a first horizontal portion of the third layer above a surface of the semiconductor substrate between the first and second gate electrode structures.

摘要翻译： 通常，本文公开的主题涉及复杂的半导体器件及其形成方法，其中相邻栅电极之间的间距被积极地缩放，并且其中可以利用自对准接触元件来避免通常与 使用通常可获得的光刻技术形成的窄接触元件。 一个说明性实施例包括在半导体衬底之上形成第一和第二栅电极结构，然后形成与第一和第二栅电极结构中的每一个的侧壁相邻或接触的第一电介质材料的第一层。 说明性方法还包括在第一层上形成第二电介质材料的第二层的步骤，随后在第二层上形成第三电介质材料的第三层，其中形成第三层还包括形成第一水平部分 在第一和第二栅电极结构之间的半导体衬底的表面上方的第三层。

公开(公告)号：US20120211808A1

公开(公告)日：2012-08-23

申请号：US13372837

申请日：2012-02-14

申请人： Andy Wei ,  Peter Baars ,  Richard Carter ,  Frank Ludwig

发明人： Andy Wei ,  Peter Baars ,  Richard Carter ,  Frank Ludwig

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： When forming sophisticated semiconductor devices, three-dimensional transistors in combination with planar transistors may be formed on the basis of a replacement gate approach and self-aligned contact elements by forming the semiconductor fins in an early manufacturing stage, i.e., upon forming shallow trench isolations, wherein the final electrically effective height of the semiconductor fins may be adjusted after the provision of self-aligned contact elements and during the replacement gate approach.

摘要翻译： 当形成复杂的半导体器件时，与平面晶体管组合的三维晶体管可以通过在早期制造阶段中形成半导体翅片（即，在形成浅沟槽隔离时）基于替代栅极接近和自对准接触元件而形成 其中半导体翅片的最终电有效高度可以在提供自对准接触元件之后和在更换栅极接近期间被调整。

公开(公告)号：US08652889B2

公开(公告)日：2014-02-18

申请号：US13372837

申请日：2012-02-14

申请人： Andy Wei ,  Peter Baars ,  Richard Carter ,  Frank Ludwig

发明人： Andy Wei ,  Peter Baars ,  Richard Carter ,  Frank Ludwig

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/66

CPC分类号： H01L21/823807 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： When forming sophisticated semiconductor devices, three-dimensional transistors in combination with planar transistors may be formed on the basis of a replacement gate approach and self-aligned contact elements by forming the semiconductor fins in an early manufacturing stage, i.e., upon forming shallow trench isolations, wherein the final electrically effective height of the semiconductor fins may be adjusted after the provision of self-aligned contact elements and during the replacement gate approach.

摘要翻译： 当形成复杂的半导体器件时，与平面晶体管组合的三维晶体管可以通过在早期制造阶段中形成半导体翅片（即，在形成浅沟槽隔离时）基于替代栅极接近和自对准接触元件而形成 其中半导体翅片的最终电有效高度可以在提供自对准接触元件之后和在更换栅极接近期间被调整。

公开(公告)号：US20120211837A1

公开(公告)日：2012-08-23

申请号：US13372604

申请日：2012-02-14

申请人： Peter Baars ,  Till Schloesser ,  Frank Jakubowski ,  Andy Wei ,  Richard Carter ,  Matthias Schaller

发明人： Peter Baars ,  Till Schloesser ,  Frank Jakubowski ,  Andy Wei ,  Richard Carter ,  Matthias Schaller

IPC分类号： H01L21/28 ,  H01L21/283 ,  H01L27/088

CPC分类号： H01L21/823475 ,  H01L21/28518 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/66636 ,  H01L29/7848

摘要： When forming sophisticated semiconductor devices, a replacement gate approach may be applied in combination with a self-aligned contact regime by forming the self-aligned contacts prior to replacing the placeholder material of the gate electrode structures.

摘要翻译： 当形成复杂的半导体器件时，可以在替换栅极电极结构的占位符材料之前形成自对准触点，将替代栅极方法与自对准接触方式结合使用。

公开(公告)号：US20120153398A1

公开(公告)日：2012-06-21

申请号：US12974037

申请日：2010-12-21

申请人： Peter Baars ,  Richard Carter ,  Andy Wei

发明人： Peter Baars ,  Richard Carter ,  Andy Wei

IPC分类号： H01L27/092 ,  H01L21/8234 ,  H01L29/772 ,  H01L21/28

CPC分类号： H01L27/092 ,  H01L21/28512 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/28 ,  H01L23/485 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7847 ,  H01L2924/0002 ,  H01L2924/00

摘要： Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein the pitch between adjacent gate electrodes is aggressively scaled, and wherein self-aligning contact elements may be utilized to avoid the high electrical resistance levels commonly associated with narrow contact elements formed using typically available photolithography techniques. One illustrative embodiment includes forming first and second gate electrode structures above a semiconductor substrate, then forming a first layer of a first dielectric material adjacent to or in contact with the sidewalls of each of the first and second gate electrode structures. The illustrative method further includes a step of forming a second layer of a second dielectric material on the first layer, followed by forming a third layer of a third dielectric material on the second layer, wherein forming the third layer further comprises forming a first horizontal portion of the third layer above a surface of the semiconductor substrate between the first and second gate electrode structures.

摘要翻译： 通常，本文公开的主题涉及复杂的半导体器件及其形成方法，其中相邻栅电极之间的间距被积极地缩放，并且其中可以利用自对准接触元件来避免通常与 使用通常可获得的光刻技术形成的窄接触元件。 一个说明性实施例包括在半导体衬底之上形成第一和第二栅电极结构，然后形成与第一和第二栅电极结构中的每一个的侧壁相邻或接触的第一电介质材料的第一层。 说明性方法还包括在第一层上形成第二电介质材料的第二层的步骤，随后在第二层上形成第三电介质材料的第三层，其中形成第三层还包括形成第一水平部分 在第一和第二栅电极结构之间的半导体衬底的表面上方的第三层。