摘要:
A method (100) of fabricating an LED or the active regions of an LED and an LED (200). The method includes growing, depositing or otherwise providing a bottom cladding layer (208) of a selected semiconductor alloy with an adjusted bandgap provided by intentionally disordering the structure of the cladding layer (208). A first active layer (202) may be grown above the bottom cladding layer (208) wherein the first active layer (202) is fabricated of the same semiconductor alloy, with however, a partially ordered structure. The first active layer (202) will also be fabricated to include a selected n or p type doping. The method further includes growing a second active layer (204) above the first active layer (202) where the second active layer (204) Is fabricated from the same semiconductor alloy.
摘要:
A method (100) of fabricating an LED or the active regions of an LED and an LED (200). The method includes growing, depositing or otherwise providing a bottom cladding layer (208) of a selected semiconductor alloy with an adjusted bandgap provided by intentionally disordering the structure of the cladding layer (208). A first active layer (202) may be grown above the bottom cladding layer (208) wherein the first active layer (202) is fabricated of the same semiconductor alloy, with however, a partially ordered structure. The first active layer (202) will also be fabricated to include a selected n or p type doping. The method further includes growing a second active layer (204) above the first active layer (202) where the second active layer (204) Is fabricated from the same semiconductor alloy.
摘要:
Optoelectronic devices, junctions and methods of fabricating a device or junction where the emitter layer is of an indirect-band-gap material and the base layer is of a direct-band-gap material. The device or junction may have, among other structures and layers, a base layer of a first semiconductor material having a first conductivity type and further having a direct band gap and an emitter layer forming a junction with the base layer. In this embodiment, the emitter layer may be of a second semiconductor material having a second conductivity type and further having an indirect band gap. The optoelectronic device may have the semiconductor material of the emitter layer substantially lattice mismatched with the semiconductor material of the base layer in bulk form. Alternatively, the emitter layer may be substantially lattice matched with the base layer.
摘要:
High bandgap alloys for high efficiency optoelectronics are disclosed. An exemplary optoelectronic device may include a substrate, at least one Al1-xInxP layer, and a step-grade buffer between the substrate and at least one Al1-xInxP layer. The buffer may begin with a layer that is substantially lattice matched to GaAs, and may then incrementally increase the lattice constant in each sequential layer until a predetermined lattice constant of Al1-xInxP is reached.
摘要:
High bandgap alloys for high efficiency optoelectronics are disclosed. An exemplary optoelectronic device may include a substrate, at least one Al1-xInxP layer, and a step-grade buffer between the substrate and at least one Al1-xInxP layer. The buffer may begin with a layer that is substantially lattice matched to GaAs, and may then incrementally increase the lattice constant in each sequential layer until a predetermined lattice constant of Al1-xInxP is reached.
摘要:
Modeling a monolithic, multi-bandgap, tandem, solar photovoltaic converter or thermophotovoltaic converter by constraining the bandgap value for the bottom subcell to no less than a particular value produces an optimum combination of subcell bandgaps that provide theoretical energy conversion efficiencies nearly as good as unconstrained maximum theoretical conversion efficiency models, but which are more conducive to actual fabrication to achieve such conversion efficiencies than unconstrained model optimum bandgap combinations. Achieving such constrained or unconstrained optimum bandgap combinations includes growth of a graded layer transition from larger lattice constant on the parent substrate to a smaller lattice constant to accommodate higher bandgap upper subcells and at least one graded layer that transitions back to a larger lattice constant to accommodate lower bandgap lower subcells and to counter-strain the epistructure to mitigate epistructure bowing.
摘要:
Isoelectronic co-doping of semiconductor compounds and alloys with acceptors and deep donors is sued to decrease bandgap, to increase concentration of the dopant constituents in the resulting alloys, and to increase carrier mobilities lifetimes. For example, Group III-V compounds and alloys, such as GaAs and GaP, are isoelectronically co-doped with, for example, B and Bi, to customize solar cells, and other semiconductor devices. Isoelectronically co-doped Group II-VI compounds and alloys are also included.
摘要:
A method for improving the overall quantum efficiency and output voltage in solar cells using spontaneous ordered semiconductor alloy absorbers to form a DOH below the front or above the back surface of the cell.
摘要:
A multijunction, monolithic, photovoltaic (PV) cell and device (600) is provided for converting radiant energy to photocurrent and photovoltage with improved efficiency. The PV cell includes an array of subcells (602), i.e., active p/n junctions, grown on a compliant substrate, where the compliant substrate accommodates greater flexibility in matching lattice constants to adjacent semiconductor material. The lattice matched semiconductor materials are selected with appropriate band-gaps to efficiently create photovoltage from a larger portion of the solar spectrum. Subcell strings (601, 603) from multiple PV cells are voltage matched to provide high output PV devices. A light emitting cell and device is also provided having monolithically grown red-yellow and green emission subcells and a mechanically stacked blue emission subcell.
摘要:
A monolithic multi-junction (tandem) photo-voltaic (PV) device includes one or more PV subcells epitaxially formed on a compliant silicon substrate (102). The compliant silicon substrate (102) includes a base silicon layer (108), a conductive perovskite layer (112), and an oxide layer (110) interposed between the base silicon layer (108) and the conductive perovskite layer (112). A PV subcell is formed within the base silicon layer (108) of the conductive silicon substrate (102). The conductive perovskite layer (112) facilitates the conduction of charge carriers between the PV subcell formed in the compliant silicon substrate (102) and the one or more PV subcells formed on the compliant silicon substrate (102).