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1.发明授权Method and apparatus for an I/O controller to alert an external system management controller 有权用于提醒外部系统管理控制器的I / O控制器的方法和装置公开(公告)号：US07103692B2
公开(公告)日：2006-09-05
申请号：US10295543
申请日：2002-11-14
CPC分类号： G06F13/24
摘要： Embodiments of the present invention provide a method and apparatus to allow an I/O controller to alert an external controller using an enhanced SMBus implementation that enables bi-directional capability on SMBALERT#. I/O controller includes an auxiliary control register and alert output enable (AOEN) register. When host sets AOE bit in auxiliary control register, SMBALERT# signal is configured as an output signal with bi-directional functionality. External controller uses an interface command to write to AOEN register and determine events/conditions it wants to be alerted on. SMBALERT# is activated in response to a detected event/condition. In response to SMBALERT#, external controller determines the alert generation condition using byte read commands on the system management bus, and clears SMBALERT#.
摘要翻译： 本发明的实施例提供一种允许I / O控制器使用能够在SMBALERT＃上实现双向能力的增强型SMBus实现来向外部控制器发出警报的方法和装置。 I / O控制器包括辅助控制寄存器和报警输出使能（AOEN）寄存器。 当主机在辅助控制寄存器中设置AOE位时，SMBALERT＃信号被配置为具有双向功能的输出信号。 外部控制器使用接口命令写入AOEN寄存器，并确定要发送的事件/条件。 响应于检测到的事件/条件，SMBALERT＃被激活。 响应SMBALERT＃，外部控制器使用系统管理总线上的字节读取命令确定警报生成条件，并清除SMBALERT＃。
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2.发明授权Method and apparatus to permit external access to internal configuration registers 有权允许外部访问内部配置寄存器的方法和设备公开(公告)号：US06973526B2
公开(公告)日：2005-12-06
申请号：US10183641
申请日：2002-06-28
申请人： John P. Lee , Atul Kwatra , Aniruddha P. Joshi
发明人： John P. Lee , Atul Kwatra , Aniruddha P. Joshi
CPC分类号： G06F13/4004 , G06F2213/0024
摘要： Access to internal configuration registers on a computer system's chipset using an external micro-controller is provided. A SMB configuration read command including a register address may be received from an external micro-controller. Access to an internal bus may be requested from a bus arbiter. If internal bus access is granted, the SMB configuration read command may be forwarded to a device including the identified register address using the internal bus. In response to the SMB configuration read command, configuration register values from the device may be received. The configuration register values may be forwarded to the external micro-controller.
摘要翻译： 提供使用外部微控制器访问计算机系统芯片组上的内部配置寄存器。 可以从外部微控制器接收包括寄存器地址的SMB配置读取命令。 可以从总线仲裁器请求访问内部总线。 如果内部总线访问被授予，SMB配置读取命令可以使用内部总线转发到包括所识别的寄存器地址的设备。 响应于SMB配置读命令，可以接收来自设备的配置寄存器值。 配置寄存器值可以转发到外部微控制器。
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3.发明授权Method, system, and apparatus to decrease CPU temperature through I/O bus throttling 有权通过I / O总线调节降低CPU温度的方法，系统和设备公开(公告)号：US07596638B2
公开(公告)日：2009-09-29
申请号：US10873779
申请日：2004-06-21
IPC分类号： G06F3/00
CPC分类号： G06F1/324 , G06F1/206 , G06F1/3209 , Y02D10/126
摘要： A method, apparatus, and system are disclosed. In one embodiment the method detects a temperature event in a processor and then modifies the bus frequency of an I/O bus coupled to an I/O controller hub in response to the temperature event. In another embodiment, the apparatus includes a temperature detection unit that detects a temperature event in a processor and, additionally, a bus frequency modification unit that will modify the bus frequency of an I/O bus in response to the temperature event.
摘要翻译： 公开了一种方法，装置和系统。 在一个实施例中，该方法检测处理器中的温度事件，然后响应于温度事件修改耦合到I / O控制器集线器的I / O总线的总线频率。 在另一个实施例中，该装置包括温度检测单元，其检测处理器中的温度事件，另外还包括总线频率修改单元，其将响应于温度事件修改I / O总线的总线频率。
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4.发明授权Apparatus and method for maintaining data integrity following parity error detection 有权用于在奇偶校验错误检测之后维持数据完整性的装置和方法公开(公告)号：US07251755B2
公开(公告)日：2007-07-31
申请号：US10779140
申请日：2004-02-13
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0745 , G06F11/076 , G06F11/0772 , G06F11/079
摘要： In some embodiments, a method and apparatus for maintaining data integrity following parity error detection are described. In one embodiment, the method includes the blockage of bus transactions in response to detection of a parity error. Once bus transactions are suspended, a parity error handler routine is invoked to perform parity error recovery according to stored transaction information regarding an error bus transaction of the detected parity error. In one embodiment, the stored information includes a bus master that caused the error, as well as an address associated with the corrupt data for which the parity error was asserted. In one embodiment, data logging is performed to track the bus masters associated with error bus transactions to enable identification of problematic or old hardware devices. Other embodiments are described and claims.
摘要翻译： 在一些实施例中，描述了用于在奇偶校验错误检测之后维持数据完整性的方法和装置。 在一个实施例中，该方法包括响应于奇偶校验错误的检测而阻塞总线事务。 一旦暂停总线事务，根据存储的关于检测到的奇偶校验错误的错误总线事务的事务信息，调用奇偶校验错误处理程序来执行奇偶校验错误恢复。 在一个实施例中，所存储的信息包括导致错误的总线主机，以及与被断言奇偶校验错误的损坏数据相关联的地址。 在一个实施例中，执行数据记录以跟踪与错误总线事务相关联的总线主控器，以便能够识别有问题的或旧的硬件设备。 其他实施例被描述和权利要求。
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公开(公告)号：US07213094B2
公开(公告)日：2007-05-01
申请号：US10780372
申请日：2004-02-17
IPC分类号： G06F13/36
CPC分类号： G06F13/4027
摘要： Method and apparatus for supporting multi-function PCI devices in PCI bridges. Respective pre-fetch buffers are allocated in response to respective initial data transfer requests issued by a multi-function PCI device. A programmable buffer fill watermark is set up for each pre-fetch buffer. While a portion of data corresponding to the data transfer requests fill the pre-fetch buffers, the fill level of each buffer is monitored to determine if it meets or exceeds its buffer fill watermark. In response to such a condition, the multi-function PCI device is connected to the PCI bridge and a virtual buffer is mapped to the pre-fetch buffer. The pre-fetch buffer is then emptied. During subsequent data transfers, each of the pre-fetch buffer becomes filled, the PCI device is connected, and the virtual buffer is mapped to the filled buffer. The process is continued until all data corresponding to the original data transfer request is received by the multi-function PCI device.
摘要翻译： 支持PCI桥中多功能PCI设备的方法和装置。 响应于由多功能PCI设备发出的各自的初始数据传送请求分配各自的预取缓冲器。 为每个预取缓冲区设置可编程缓冲区填充水印。 虽然对应于数据传输请求的一部分数据填充预取缓冲器，但是监视每个缓冲器的填充级别以确定其是否满足或超过其缓冲区填充水印。 响应于这种情况，多功能PCI设备连接到PCI桥，虚拟缓冲器被映射到预取缓冲器。 然后将预取缓冲区清空。 在随后的数据传输期间，每个预取缓冲区都被填满，PCI设备被连接，虚拟缓冲区被映射到已填充的缓冲区。 该过程一直持续到多功能PCI设备接收到与原始数据传送请求相对应的所有数据。
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6.发明授权Method and apparatus for generating traffic in an electronic bridge via a local controller 有权用于经由本地控制器在电子桥中产生流量的方法和装置公开(公告)号：US07346725B2
公开(公告)日：2008-03-18
申请号：US11462264
申请日：2006-08-03
IPC分类号： G06F13/00
CPC分类号： G06F13/4004
摘要： A system to monitor performance of a computing device includes a first bridge to interface with a first set of devices, and a second bridge to interface with a second set of devices. Configuration registers store configuration data associated with the second set of devices, and are accessible through the second bridge. A hub interface allows data to transfer downstream from the first bridge to the second bridge, and allows data to transfer upstream from the second bridge to the first bridge. A controller, external to the first and second bridges, accesses the configuration registers via the second bridge. A logic device allows the second bridge to send data to, and receive data from, the controller.
摘要翻译： 监视计算设备性能的系统包括与第一组设备进行接口的第一桥接器和与第二组设备接口的第二桥接器。 配置寄存器存储与第二组设备相关联的配置数据，并且可通过第二桥接器访问。 集线器接口允许数据从第一桥下游传输到第二桥，并且允许数据从第二桥上游传输到第一桥。 在第一和第二桥外部的控制器通过第二桥接器访问配置寄存器。 逻辑设备允许第二桥接器向控制器发送数据并从控制器接收数据。
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7.发明授权公开(公告)号：US06944796B2
公开(公告)日：2005-09-13
申请号：US10180508
申请日：2002-06-27
CPC分类号： G06F11/0772 , G06F11/0745 , G06F11/2268 , G06F11/349
摘要： Embodiments of the present invention provide a system event log for a computer system. The system event log may comprise a RAM coupled to a system bus. The system event log may be configured to record information in the RAM corresponding to bus transactions on the system bus. The information may be used to de-bug system problems.
摘要翻译： 本发明的实施例提供了一种用于计算机系统的系统事件日志。 系统事件日志可以包括耦合到系统总线的RAM。 可以将系统事件日志配置为在RAM中记录与系统总线上的总线事务相对应的信息。 该信息可能被用来解决系统问题。
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8.发明授权Method, apparatus, and system for generating serial interrupt requests (IRQ) with power savings 失效用于生成具有省电功能的串行中断请求（IRQ）的方法，装置和系统公开(公告)号：US06898651B2
公开(公告)日：2005-05-24
申请号：US10143165
申请日：2002-05-10
摘要： According to one embodiment of the invention, a first signal line is provided for a serial interface unit (SIU) of an I/O controller to report interrupt requests to an interrupt controller. In one embodiment, a transition of the first signal line from a first level (e.g., low level or logic 0) to a second level (e.g., high level or logic 1) indicates a pending interrupt to the interrupt controller. A pull up resistor is provided to pull the first signal line to the second level when the first signal line is not driven by the SIU. In response to detecting an interrupt request initiated by an I/O device, a transition from the first level to the second level is generated on the first signal line for a predetermined duration to report the pending interrupt request to the interrupt controller.
摘要翻译： 根据本发明的一个实施例，为I / O控制器的串行接口单元（SIU）提供第一信号线，以向中断控制器报告中断请求。 在一个实施例中，第一信号线从第一电平（例如，低电平或逻辑0）到第二电平（例如，高电平或逻辑1）的转换指示到中断控制器的待决中断。 当第一信号线不由SIU驱动时，提供上拉电阻器将第一信号线拉到第二电平。 响应于检测到由I / O设备发起的中断请求，在第一信号线上产生从第一电平到第二电平的转换预定的持续时间以向中断控制器报告等待中断请求。
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公开(公告)号：US06646686B1
公开(公告)日：2003-11-11
申请号：US09666942
申请日：2000-09-21
IPC分类号： H04N974
CPC分类号： H04N5/44504 , G09G5/377 , G09G5/391 , G09G2310/0224 , G09G2340/10 , G09G2340/125 , H04N21/42653
摘要： Alpha values associated with video mixing operations are sent to a memory on a low pin count bus. The memory is accessible to a video mixer, which retrieves the alpha values to perform a mixing operation. The alpha values for a field are sent to the memory during the field time for a previous field rather than during the vertical blanking interval. The alpha values may be compressed prior to transmission.
摘要翻译： 与视频混合操作相关联的Alpha值在低引脚数总线上发送到存储器。 视频混合器可访问存储器，视频混合器检索Alpha值以执行混合操作。 字段的alpha值在前一个字段的字段时间内发送到存储器，而不是在垂直消隐间隔期间。 alpha值可能在传输之前被压缩。
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公开(公告)号：US07411631B1
公开(公告)日：2008-08-12
申请号：US09583432
申请日：2000-05-31
CPC分类号： H04N5/63 , G06F1/3203
摘要： A processor-based system may be operated in an effectively “always on” condition. The system may transition from a lower power consumption state to a higher power consumption state in response to the first operation of a power button. In response to a second operation of the power button, the system transitions from the higher power consumption state to the lower power consumption state. However, unless the system is unplugged, the system remains in a power consuming state even when the power button is repeatedly operated.
摘要翻译： 基于处理器的系统可以有效地“始终处于”状态运行。 响应于电源按钮的第一操作，系统可以从较低功耗状态转换到较高功耗状态。 响应于电源按钮的第二操作，系统从较高功耗状态转换到较低功耗状态。 然而，除非系统被拔掉，即使电源按钮被重复操作，系统仍然处于耗电状态。
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