公开(公告)号：US08148052B2

公开(公告)日：2012-04-03

申请号：US12514777

申请日：2007-11-13

申请人： Anja Monique Vanleenhove ,  Peter Dirksen ,  David Van Steenwinckel ,  Gerben Doornbos ,  Casper Juffermans ,  Mark Van Dal

发明人： Anja Monique Vanleenhove ,  Peter Dirksen ,  David Van Steenwinckel ,  Gerben Doornbos ,  Casper Juffermans ,  Mark Van Dal

IPC分类号： G03F7/26

CPC分类号： G03F7/0035 ,  G03F7/11 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

摘要： A method of forming a pattern in at least one device layer in or on a substrate comprises: coating the device layer with a first photoresist layer; exposing the first photoresist using a first mask; developing the first photoresist layer to form a first pattern on the substrate; coating the substrate with a protection layer; treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render the changed protection layer substantially immune to a subsequent exposure and/or developing step; coating the substrate with a second photoresist layer; exposing the second photoresist layer using a second mask; and developing the second photoresist layer to form a second pattern on the substrate without significantly affecting the first pattern in the first photoresist layer, wherein the first and second patterns together define interspersed features having a spatial frequency greater than that of the features defined in each of the first and second patterns separately. The process has particular utility in defining source, drain and fin features of finFET devices with a smaller feature size than otherwise achievable with the prevailing lithography tools.

摘要翻译： 在衬底中或衬底上的至少一个器件层中形成图案的方法包括：用第一光致抗蚀剂层涂覆器件层; 使用第一掩模曝光第一光致抗蚀剂; 显影第一光致抗蚀剂层以在基底上形成第一图案; 用保护层涂覆基板; 处理保护层以在其中与第一光致抗蚀剂接触的地方发生变化，使得改变的保护层基本上不受随后的曝光和/或显影步骤的影响; 用第二光致抗蚀剂层涂覆基板; 使用第二掩模曝光所述第二光致抗蚀剂层; 并且显影所述第二光致抗蚀剂层以在所述基板上形成第二图案，而不会显着影响所述第一光致抗蚀剂层中的所述第一图案，其中所述第一和第二图案一起限定散布特征，其空间频率大于 第一和第二模式分开。 该方法在定义具有较小的特征尺寸的finFET器件的源极，漏极和鳍片特征方面具有特别的用途，而与主要的光刻工具不同。

公开(公告)号：US20100028809A1

公开(公告)日：2010-02-04

申请号：US12514777

申请日：2007-11-13

申请人： Anja Monique Vanleenhove ,  Peter Dirksen ,  David Van Steenwinckel ,  Gerben Doornbos ,  Casper Juffermans ,  Mark Van Dal

发明人： Anja Monique Vanleenhove ,  Peter Dirksen ,  David Van Steenwinckel ,  Gerben Doornbos ,  Casper Juffermans ,  Mark Van Dal

IPC分类号： G03F7/20

CPC分类号： G03F7/0035 ,  G03F7/11 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

摘要： A method of forming a pattern in at least one device layer in or on a substrate comprises: coating the device layer with a first photoresist layer; exposing the first photoresist using a first mask; developing the first photoresist layer to form a first pattern on the substrate; coating the substrate with a protection layer; treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render the changed protection layer substantially immune to a subsequent exposure and/or developing step; coating the substrate with a second photoresist layer; exposing the second photoresist layer using a second mask; and developing the second photoresist layer to form a second pattern on the substrate without significantly affecting the first pattern in the first photoresist layer, wherein the first and second patterns together define interspersed features having a spartial frequency greater than that of the features defined in each of the first and second patterns separately. The process has particular utility in defining source, drain and fin features of finFET devices with a smaller feature size than otherwise achievable with the prevailing lithography tools.

摘要翻译： 在衬底中或衬底上的至少一个器件层中形成图案的方法包括：用第一光致抗蚀剂层涂覆器件层; 使用第一掩模曝光第一光致抗蚀剂; 显影第一光致抗蚀剂层以在基底上形成第一图案; 用保护层涂覆基板; 处理保护层以在其中与第一光致抗蚀剂接触的地方发生变化，使得改变的保护层基本上不受随后的曝光和/或显影步骤的影响; 用第二光致抗蚀剂层涂覆基板; 使用第二掩模曝光所述第二光致抗蚀剂层; 并且显影所述第二光致抗蚀剂层以在所述衬底上形成第二图案，而不会显着影响所述第一光致抗蚀剂层中的所述第一图案，其中所述第一和第二图案一起限定散布特征，其间隔频率大于每个 第一和第二模式分开。 该方法在定义具有较小的特征尺寸的finFET器件的源极，漏极和鳍片特征方面具有特别的用途，而与主要的光刻工具不同。

公开(公告)号：US09766195B2

公开(公告)日：2017-09-19

申请号：US13471609

申请日：2012-05-15

申请人： Roel Daamen ,  Casper Juffermans ,  Josephus Franciscus Antonius Maria Guelen ,  Robertus Antonius Maria Wolters

发明人： Roel Daamen ,  Casper Juffermans ,  Josephus Franciscus Antonius Maria Guelen ,  Robertus Antonius Maria Wolters

IPC分类号： H01L27/20 ,  H01L41/22 ,  G01N27/22 ,  G01R31/28

CPC分类号： G01N27/223 ,  G01R31/2881 ,  G01R31/2884

摘要： Disclosed is an integrated circuit (IC) comprising a substrate (10) carrying a plurality of circuit elements; a metallization stack (12, 14, 16) interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising at least one sensor electrode portion (20) and a bond pad portion (22), at least the at least one sensor electrode portion of said patterned upper metallization layer being covered by a moisture barrier film (23); a passivation stack (24, 26, 28) covering the metallization stack, said passivation stack comprising a first trench (32) exposing the at least one sensor electrode portion and a second trench (34) exposing the bond pad portion; said first trench being filled with a sensor active material (36). A method of manufacturing such an IC is also disclosed.

公开(公告)号：US20120299126A1

公开(公告)日：2012-11-29

申请号：US13471609

申请日：2012-05-15

申请人： Roel Daamen ,  Casper Juffermans ,  Josephus Franciscus Antonius Maria Guelen ,  Robertus Antonius Maria Wolters

发明人： Roel Daamen ,  Casper Juffermans ,  Josephus Franciscus Antonius Maria Guelen ,  Robertus Antonius Maria Wolters

IPC分类号： H01L27/20 ,  H01L41/22

CPC分类号： G01N27/223 ,  G01R31/2881 ,  G01R31/2884

摘要： Disclosed is an integrated circuit (IC) comprising a substrate (10) carrying a plurality of circuit elements; a metallization stack (12, 14, 16) interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising at least one sensor electrode portion (20) and a bond pad portion (22), at least the at least one sensor electrode portion of said patterned upper metallization layer being covered by a moisture barrier film (23); a passivation stack (24, 26, 28) covering the metallization stack, said passivation stack comprising a first trench (32) exposing the at least one sensor electrode portion and a second trench (34) exposing the bond pad portion; said first trench being filled with a sensor active material (36). A method of manufacturing such an IC is also disclosed.

摘要翻译： 公开了一种包括承载多个电路元件的基板（10）的集成电路（IC） 互连所述电路元件的金属化堆叠（12,14,16），所述金属化堆叠包括图案化的上部金属化层，其包括至少一个传感器电极部分（20）和接合焊盘部分（22），至少所述至少一个传感器 所述图案化上金属化层的电极部分被防潮膜（23）覆盖; 覆盖所述金属化堆叠的钝化堆叠（24,26,28），所述钝化堆叠包括暴露所述至少一个传感器电极部分的第一沟槽（32）和暴露所述接合焊盘部分的第二沟槽（34） 所述第一沟槽填充有传感器活性材料（36）。 还公开了制造这种IC的方法。