公开(公告)号：US08148052B2

公开(公告)日：2012-04-03

申请号：US12514777

申请日：2007-11-13

申请人： Anja Monique Vanleenhove ,  Peter Dirksen ,  David Van Steenwinckel ,  Gerben Doornbos ,  Casper Juffermans ,  Mark Van Dal

发明人： Anja Monique Vanleenhove ,  Peter Dirksen ,  David Van Steenwinckel ,  Gerben Doornbos ,  Casper Juffermans ,  Mark Van Dal

IPC分类号： G03F7/26

CPC分类号： G03F7/0035 ,  G03F7/11 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

摘要： A method of forming a pattern in at least one device layer in or on a substrate comprises: coating the device layer with a first photoresist layer; exposing the first photoresist using a first mask; developing the first photoresist layer to form a first pattern on the substrate; coating the substrate with a protection layer; treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render the changed protection layer substantially immune to a subsequent exposure and/or developing step; coating the substrate with a second photoresist layer; exposing the second photoresist layer using a second mask; and developing the second photoresist layer to form a second pattern on the substrate without significantly affecting the first pattern in the first photoresist layer, wherein the first and second patterns together define interspersed features having a spatial frequency greater than that of the features defined in each of the first and second patterns separately. The process has particular utility in defining source, drain and fin features of finFET devices with a smaller feature size than otherwise achievable with the prevailing lithography tools.

摘要翻译： 在衬底中或衬底上的至少一个器件层中形成图案的方法包括：用第一光致抗蚀剂层涂覆器件层; 使用第一掩模曝光第一光致抗蚀剂; 显影第一光致抗蚀剂层以在基底上形成第一图案; 用保护层涂覆基板; 处理保护层以在其中与第一光致抗蚀剂接触的地方发生变化，使得改变的保护层基本上不受随后的曝光和/或显影步骤的影响; 用第二光致抗蚀剂层涂覆基板; 使用第二掩模曝光所述第二光致抗蚀剂层; 并且显影所述第二光致抗蚀剂层以在所述基板上形成第二图案，而不会显着影响所述第一光致抗蚀剂层中的所述第一图案，其中所述第一和第二图案一起限定散布特征，其空间频率大于 第一和第二模式分开。 该方法在定义具有较小的特征尺寸的finFET器件的源极，漏极和鳍片特征方面具有特别的用途，而与主要的光刻工具不同。

公开(公告)号：US20100028809A1

公开(公告)日：2010-02-04

申请号：US12514777

申请日：2007-11-13

申请人： Anja Monique Vanleenhove ,  Peter Dirksen ,  David Van Steenwinckel ,  Gerben Doornbos ,  Casper Juffermans ,  Mark Van Dal

发明人： Anja Monique Vanleenhove ,  Peter Dirksen ,  David Van Steenwinckel ,  Gerben Doornbos ,  Casper Juffermans ,  Mark Van Dal

IPC分类号： G03F7/20

CPC分类号： G03F7/0035 ,  G03F7/11 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

摘要： A method of forming a pattern in at least one device layer in or on a substrate comprises: coating the device layer with a first photoresist layer; exposing the first photoresist using a first mask; developing the first photoresist layer to form a first pattern on the substrate; coating the substrate with a protection layer; treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render the changed protection layer substantially immune to a subsequent exposure and/or developing step; coating the substrate with a second photoresist layer; exposing the second photoresist layer using a second mask; and developing the second photoresist layer to form a second pattern on the substrate without significantly affecting the first pattern in the first photoresist layer, wherein the first and second patterns together define interspersed features having a spartial frequency greater than that of the features defined in each of the first and second patterns separately. The process has particular utility in defining source, drain and fin features of finFET devices with a smaller feature size than otherwise achievable with the prevailing lithography tools.

摘要翻译： 在衬底中或衬底上的至少一个器件层中形成图案的方法包括：用第一光致抗蚀剂层涂覆器件层; 使用第一掩模曝光第一光致抗蚀剂; 显影第一光致抗蚀剂层以在基底上形成第一图案; 用保护层涂覆基板; 处理保护层以在其中与第一光致抗蚀剂接触的地方发生变化，使得改变的保护层基本上不受随后的曝光和/或显影步骤的影响; 用第二光致抗蚀剂层涂覆基板; 使用第二掩模曝光所述第二光致抗蚀剂层; 并且显影所述第二光致抗蚀剂层以在所述衬底上形成第二图案，而不会显着影响所述第一光致抗蚀剂层中的所述第一图案，其中所述第一和第二图案一起限定散布特征，其间隔频率大于每个 第一和第二模式分开。 该方法在定义具有较小的特征尺寸的finFET器件的源极，漏极和鳍片特征方面具有特别的用途，而与主要的光刻工具不同。

公开(公告)号：US20130256784A1

公开(公告)日：2013-10-03

申请号：US13436322

申请日：2012-03-30

申请人： Georgios Vellianitis ,  Mark Van Dal ,  Blandine Duriez

发明人： Georgios Vellianitis ,  Mark Van Dal ,  Blandine Duriez

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/76264 ,  H01L21/30604 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7853

摘要： A device includes a semiconductor substrate, and a channel region of a transistor over the semiconductor substrate. The channel region includes a semiconductor material. An air gap is disposed under and aligned to the channel region, with a bottom surface of the channel region exposed to the air gap. Insulation regions are disposed on opposite sides of the air gap, wherein a bottom surface of the channel region is higher than top surfaces of the insulation regions. A gate dielectric of the transistor is disposed on a top surface and sidewalls of the channel region. A gate electrode of the transistor is over the gate dielectric.

摘要翻译： 一种器件包括半导体衬底和半导体衬底上的晶体管的沟道区域。 沟道区域包括半导体材料。 气隙设置在通道区域的下方并与之对准，通道区域的底表面暴露于气隙。 绝缘区域设置在气隙的相对侧上，其中沟道区域的底表面高于绝缘区域的顶表面。 晶体管的栅极电介质设置在沟道区的顶表面和侧壁上。 晶体管的栅电极在栅极电介质上方。

公开(公告)号：US20090302389A1

公开(公告)日：2009-12-10

申请号：US12066707

申请日：2006-09-11

申请人： Robert Lander ,  Mark Van Dal ,  Jacob Hooker

发明人： Robert Lander ,  Mark Van Dal ,  Jacob Hooker

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28097 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/78

摘要： A method is described for forming gate structures with different metals on a single substrate. A thin semiconductor layer (26) is formed over gate dielectric (24) and patterned to be present in a first region (16) not a second region (18). Then, metal (30) is deposited and patterned to be present in the second region not the first. Then, a fully suicided gate process is carried out to result in a fully suicided gate structure in the first region and a gate structure in the second region including the fully suicided gate structure above the deposited metal (30).

摘要翻译： 描述了在单个衬底上形成具有不同金属的栅极结构的方法。 在栅极电介质（24）上形成薄的半导体层（26），并被图案化以存在于不是第二区域（18）的第一区域（16）中。 然后，金属（30）被沉积并图案化以存在于不是第一区域的第二区域中。 然后，进行完全自动的栅极处理，以在第一区域中产生完全自述的栅极结构，并且在第二区域中的栅极结构包括沉积金属（30）上方的完全自蚀的栅极结构。

公开(公告)号：US07791140B2

公开(公告)日：2010-09-07

申请号：US12278629

申请日：2007-02-02

申请人： Mark Van Dal ,  Radu Surdeanu

发明人： Mark Van Dal ,  Radu Surdeanu

IPC分类号： H01L27/12 ,  H01L21/62 ,  H01L21/20

CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/7856

摘要： A double-gate FinFET and methods for its manufacture are provided. The FinFET includes first and second gates (72, 74) adjacent respective sides of the fin (20), with at least a portion of the first gate facing the fin being formed of polycrystalline silicon, and at least a portion of the second gate facing the fin being formed of a metal silicide compound. The different compositions of the two gates provide different respective work functions to reduce short channel effects.

摘要翻译： 提供了双栅FinFET及其制造方法。 FinFET包括与翅片（20）的相应侧面相邻的第一和第二栅极（72,74），其中第一栅极的面对鳍片的至少一部分由多晶硅形成，并且第二栅极的至少一部分面向 翅片由金属硅化物化合物形成。 两个门的不同组成提供不同的各自的功能来减少短路效应。

公开(公告)号：US20100044760A1

公开(公告)日：2010-02-25

申请号：US12514940

申请日：2007-11-13

申请人： Gilberto Curatola ,  Mark Van Dal ,  Jan Sonsky

发明人： Gilberto Curatola ,  Mark Van Dal ,  Jan Sonsky

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7391 ,  H01L29/66356

摘要： An impact ionisation MOSFET is formed with the offset from the gate to one of the source/drain regions disposed vertically within the device structure rather than horizontally. The semiconductor device comprises a first source/drain region having a first doping level; a second source/drain region having a second doping level and of opposite dopant type to the first source/drain region, the first and second source/drain regions being laterally separated by an intermediate region having a doping level less than either of the first and second doping levels; a gate electrode electrically insulated from, and disposed over, the intermediate region, the first and second source/drain regions being laterally aligned with the gate electrode; where the entire portion of the first source/drain region that forms a boundary with the intermediate region is separated vertically from the top of the intermediate region.

摘要翻译： 冲击电离MOSFET形成为从栅极偏移到垂直设置在器件结构内而不是水平的源/漏区之一。 半导体器件包括具有第一掺杂水平的第一源极/漏极区域; 具有第二掺杂水平并且与第一源极/漏极区相反的掺杂剂类型的第二源极/漏极区域，第一和第二源极/漏极区域由具有小于第一和/或第二源极/ 第二掺杂水平; 与所述中间区域电绝缘并设置在所述中间区域上的栅电极，所述第一和第二源极/漏极区域与所述栅电极横向对准; 其中形成与中间区域的边界的第一源极/漏极区域的整个部分与中间区域的顶部垂直地分离。

公开(公告)号：US20090242987A1

公开(公告)日：2009-10-01

申请号：US12278629

申请日：2007-02-02

申请人： Mark Van Dal ,  Radu Surdeanu

发明人： Mark Van Dal ,  Radu Surdeanu

IPC分类号： H01L27/12 ,  H01L21/762 ,  H01L21/20

CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/7856

摘要： A double-gate FinFET and methods for its manufacture are provided. The FinFET includes first and second gates (72, 74) adjacent respective sides of the fin (20), with at least a portion of the first gate facing the fin being formed of polycrystalline silicon, and at least a portion of the second gate facing the fin being formed of a metal suicide compound. The different compositions of the two gates provide different respective work functions to reduce short channel effects.

摘要翻译： 提供了双栅FinFET及其制造方法。 FinFET包括与翅片（20）的相应侧面相邻的第一和第二栅极（72,74），其中第一栅极的面对鳍片的至少一部分由多晶硅形成，并且第二栅极的至少一部分面向 翅片由金属硅化物形成。 两个门的不同组成提供不同的各自的功能来减少短路效应。

公开(公告)号：US20080258186A1

公开(公告)日：2008-10-23

申请号：US12158104

申请日：2006-12-12

申请人： Radu Surdeanu ,  Mark Van Dal

发明人： Radu Surdeanu ,  Mark Van Dal

IPC分类号： H01L29/00 ,  H01L21/8236

CPC分类号： H01L21/02667 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2022 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/41775 ,  H01L29/66636 ,  H01L29/78654

摘要： A silicon on insulator device has a silicon layer (10) over a buried insulating layer (12). A nickel layer is deposited over a gate (16), on sidewall spacers (22) on the sides of the gate (16), and in a cavity on both sides of the gate (16) in the silicon layer (10). A doped amorphous silicon layer fills the cavity. Annealing then takes place which forms polysilicon (40) over the sidewall spacers (22) and gate (16), but where the nickel is adjacent to single crystal silicon (10) a layer of NiSi (44) migrates to the surface leaving doped single crystal silicon (42) behind, forming in one step a source, drain, and source and drain contacts.

摘要翻译： 硅绝缘体器件在掩埋绝缘层（12）上方具有硅层（10）。 镍层沉积在栅极（16）上，位于栅极（16）侧面上的侧壁间隔物（22）上，并沉积在硅层（10）中的栅极（16）两侧的空腔中。 掺杂的非晶硅层填充空腔。 然后发生在侧壁间隔物（22）和栅极（16）上形成多晶硅（40）的退火，但是当镍与单晶硅（10）相邻时，一层NiSi（44）迁移到表面，离开掺杂单 晶体硅（42）后面，形成一个源极，漏极以及源极和漏极触点。

公开(公告)号：US20080237871A1

公开(公告)日：2008-10-02

申请号：US12093649

申请日：2006-10-27

申请人： Vijayaraghavan Madakasira ,  Prabhat Agarwal ,  Johannes Josephus Theodorus Marinus Donkers ,  Mark Van Dal

发明人： Vijayaraghavan Madakasira ,  Prabhat Agarwal ,  Johannes Josephus Theodorus Marinus Donkers ,  Mark Van Dal

IPC分类号： H01L21/768 ,  H01L21/20 ,  H01L23/532

CPC分类号： H01L21/76877 ,  H01L21/28525 ,  H01L21/76889 ,  H01L2221/1094

摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semi-conductor body (12) which is provided with at least one semiconductor element (E) and comprising a monocrystalline silicon (1) region on top of which an epitaxial silicon region (2) is formed by providing a metal silicide region (3) on the monocrystalline silicon region (1) and a low-crystallinity silicon region (4) on top of the metal silicide region (3), after which the low-crystallinity silicon region (4) is transformed by heating into the epitaxial silicon region (2) having a high-crystallinity, during which process the metal silicide region (3) is moved from the bottom of the low-crystallinity silicon region (4) to the top of the epitaxial silicon region (2). According to the invention above the level of the metal silicide region (3) an insulating layer (5) is formed which is provided with an opening (6), the low-crystallinity silicon region (4) is deposited in the opening (6) and on top of the insulating layer (5), the part (4A, 4B) of the low-crystallinity silicon region (4) on top of the insulating layer (5) is removed by a planarization process after which the epitaxial silicon region (2) is formed. In this way an epitaxial silicon region (2), preferably a nano wire (2), is simply obtained that is provided with a metal silicide contact (region) in a self-aligned manner and that can form a part of semiconductor element (E) like a transistor.

摘要翻译： 本发明涉及一种制造半导体器件（10）的方法，所述半导体器件（10）具有衬底（11）和半导体本体（12），所述半导体本体（12）设置有至少一个半导体元件（E）并且包括单晶硅（1）区域 通过在单晶硅区域（1）上提供金属硅化物区域（3）并且在金属硅化物区域（3）的顶部上提供低结晶度硅区域（4），在其上形成外延硅区域（2） 之后，通过加热将低结晶性硅区域（4）变换为具有高结晶度的外延硅区域（2），在该过程中，金属硅化物区域（3）从低结晶度的底部移动 硅区域（4）到外延硅区域（2）的顶部。 根据本发明，金属硅化物区域（3）的水平形成有形成有开口（6）的绝缘层（5），低结晶度硅区域（4）沉积在开口（6）中， 并且在绝缘层（5）的顶部，通过平坦化工艺除去绝缘层（5）顶部上的低结晶性硅区域（4）的部分（4A，4B），然后将外延硅 形成区域（2）。 以这种方式，简单地获得外延硅区域（2），优选纳米线（2），其以自对准的方式设置有金属硅化物接触（区域），并且可以形成半导体元件（E ）像晶体管。