公开(公告)号：US20110147842A1

公开(公告)日：2011-06-23

申请号：US12646518

申请日：2009-12-23

申请人： Annalisa Cappellani ,  Tahir Ghani ,  Kuan-Yueh Shen ,  Anand S. Murthy ,  Harry Gomez

发明人： Annalisa Cappellani ,  Tahir Ghani ,  Kuan-Yueh Shen ,  Anand S. Murthy ,  Harry Gomez

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/26506 ,  H01L21/3065 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A channel strained multi-gate transistor with low parasitic resistance and method of manufacturing the same. A gate stack may be formed over a semiconductor fin having a gate-coupled sidewall height (Hsi), an etch rate controlling dopant may be implanted into a source/drain region of the semiconductor fin adjacent to the gate stack and into a source/drain extension region of the semiconductor fin. The doped fin region may be etched to remove a thickness of the semiconductor fin equal to at least Hsi proximate a channel region and form a source/drain extension undercut. A material may be grown on the exposed semiconductor substrate to form a regrown source/drain fin region filling the source/drain extension undercut region.

摘要翻译： 具有低寄生电阻的通道应变多栅极晶体管及其制造方法。 可以在具有栅极耦合侧壁高度（Hsi）的半导体鳍片上形成栅极堆叠，蚀刻速率控制掺杂剂可以注入到与栅极堆叠相邻的半导体鳍片的源极/漏极区域中并且被注入到源极/漏极 半导体鳍片的延伸区域。 可以蚀刻掺杂散热片区域以除去等于沟道区域附近的至少Hsi的半导体鳍片的厚度并形成源极/漏极延伸底切。 可以在暴露的半导体衬底上生长材料以形成填充源极/漏极延伸底切区域的再生长源极/漏极鳍区域。

公开(公告)号：US08313999B2

公开(公告)日：2012-11-20

申请号：US12646518

申请日：2009-12-23

申请人： Annalisa Cappellani ,  Tahir Ghani ,  Kuan-Yueh Shen ,  Anand S. Murthy ,  Harry Gomez

发明人： Annalisa Cappellani ,  Tahir Ghani ,  Kuan-Yueh Shen ,  Anand S. Murthy ,  Harry Gomez

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/26506 ,  H01L21/3065 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A channel strained multi-gate transistor with low parasitic resistance and method of manufacturing the same. A gate stack may be formed over a semiconductor fin having a gate-coupled sidewall height (Hsi), an etch rate controlling dopant may be implanted into a source/drain region of the semiconductor fin adjacent to the gate stack and into a source/drain extension region of the semiconductor fin. The doped fin region may be etched to remove a thickness of the semiconductor fin equal to at least Hsi proximate a channel region and form a source/drain extension undercut. A material may be grown on the exposed semiconductor substrate to form a regrown source/drain fin region filling the source/drain extension undercut region.

摘要翻译： 具有低寄生电阻的通道应变多栅极晶体管及其制造方法。 可以在具有栅极耦合侧壁高度（Hsi）的半导体鳍片上形成栅极堆叠，蚀刻速率控制掺杂剂可以注入到与栅极堆叠相邻的半导体鳍片的源极/漏极区域中并且被注入到源极/漏极 半导体鳍片的延伸区域。 可以蚀刻掺杂散热片区域以除去等于沟道区域附近的至少Hsi的半导体鳍片的厚度并形成源极/漏极延伸底切。 可以在暴露的半导体衬底上生长材料以形成填充源极/漏极延伸底切区域的再生长源极/漏极鳍区域。

公开(公告)号：US20210409028A1

公开(公告)日：2021-12-30

申请号：US16913933

申请日：2020-06-26

申请人： Kuan-Yueh Shen ,  Nasser A. Kurd ,  John Fallin

发明人： Kuan-Yueh Shen ,  Nasser A. Kurd ,  John Fallin

IPC分类号： H03L7/099 ,  H03L7/089 ,  H03L7/189 ,  H01R13/66

摘要： Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.

公开(公告)号：US09379717B2

公开(公告)日：2016-06-28

申请号：US14129505

申请日：2013-11-08

申请人： Gennady Goltman ,  Yongping Fan ,  Kuan-Yueh Shen

发明人： Gennady Goltman ,  Yongping Fan ,  Kuan-Yueh Shen

IPC分类号： H03L7/00 ,  H03L7/08 ,  H03L7/085 ,  H03L7/089

CPC分类号： H03L7/0802 ,  H03L7/085 ,  H03L7/089 ,  H03L7/0895 ,  H03L7/093

摘要： Described is an apparatus to lower power of a charge pump. The apparatus comprises: a first delay unit to receive a reference clock, the first delay unit to provide a delayed reference clock to a first sequential unit; a second delay unit to receive a feedback clock, the second delay unit to provide a delayed feedback clock to a second sequential unit; a first logic unit to receive the reference and feedback clocks, the logic unit to perform a logical OR operation on the received reference and feedback clocks, and to generate a trigger signal for a third sequential unit; and a second logic unit to receive outputs of first and second sequential units, and to generate an output coupled to the third sequential unit.

摘要翻译： 描述了一种降低电荷泵功率的装置。 所述装置包括：第一延迟单元，用于接收参考时钟，所述第一延迟单元向第一顺序单元提供延迟的参考时钟; 第二延迟单元，用于接收反馈时钟，所述第二延迟单元向第二顺序单元提供延迟的反馈时钟; 用于接收参考和反馈时钟的第一逻辑单元，所述逻辑单元对所接收的参考和反馈时钟执行逻辑或运算，并且产生用于第三顺序单元的触发信号; 以及第二逻辑单元，用于接收第一和第二顺序单元的输出，并且产生耦合到第三顺序单元的输出。