公开(公告)号：US07662722B2

公开(公告)日：2010-02-16

申请号：US11626548

申请日：2007-01-24

申请人： Anthony K. Stamper ,  Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  William J. Murphy ,  Kunal Vaed

发明人： Anthony K. Stamper ,  Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  William J. Murphy ,  Kunal Vaed

IPC分类号： H01L21/302

CPC分类号： H01L27/0688 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/53295 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line (“FEOL”) devices are formed in a semiconductor region of the microelectronic chip, and a plurality of stacked interlevel dielectric (“ILD”) layers are formed to overlie the plurality of FEOL devices, the plurality of stacked ILD layers including a first ILD layer and a second ILD layer, where the second ILD layer is resistant to attack by a first etchant which attacks the first ILD layer. A passive device is formed to overlie at least the first ILD layer. Using the first etchant, a portion of the first ILD layer in registration with the passive device is removed to form an air gap which underlies the passive device in registration with the passive device.

摘要翻译： 提供了一种用于制造微电子芯片的方法，该微电子芯片包括覆盖气隙的诸如电感器的无源器件。 在这种方法中，在微电子芯片的半导体区域中形成多个前端（“FEOL”）器件，并且形成多个层叠的层间电介质（“ILD”）层以覆盖多个 的多个层叠的ILD层，包括第一ILD层和第二ILD层，其中第二ILD层抵抗攻击第一ILD层的第一蚀刻剂的侵袭。 形成无源器件至少覆盖第一ILD层。 使用第一蚀刻剂，除去与无源器件对准的第一ILD层的一部分，以形成与被动器件对准的无源器件下方的气隙。

公开(公告)号：US20080173976A1

公开(公告)日：2008-07-24

申请号：US11626548

申请日：2007-01-24

申请人： Anthony K. Stamper ,  Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  William J. Murphy ,  Kunal Vaed

发明人： Anthony K. Stamper ,  Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  William J. Murphy ,  Kunal Vaed

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L27/0688 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/53295 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line (“FEOL”) devices are formed in a semiconductor region of the microelectronic chip, and a plurality of stacked interlevel dielectric (“ILD”) layers are formed to overlie the plurality of FEOL devices, the plurality of stacked ILD layers including a first ILD layer and a second ILD layer, where the second ILD layer is resistant to attack by a first etchant which attacks the first ILD layer. A passive device is formed to overlie at least the first ILD layer. Using the first etchant, a portion of the first ILD layer in registration with the passive device is removed to form an air gap which underlies the passive device in registration with the passive device.

摘要翻译： 提供了一种用于制造微电子芯片的方法，该微电子芯片包括覆盖气隙的诸如电感器的无源器件。 在这种方法中，在微电子芯片的半导体区域中形成多个前端（“FEOL”）器件，并且形成多个层叠的层间电介质（“ILD”）层以覆盖多个 的多个层叠的ILD层，包括第一ILD层和第二ILD层，其中第二ILD层抵抗攻击第一ILD层的第一蚀刻剂的侵袭。 形成无源器件至少覆盖第一ILD层。 使用第一蚀刻剂，除去与无源器件对准的第一ILD层的一部分，以形成与被动器件对准的无源器件下方的气隙。

公开(公告)号：US07427550B2

公开(公告)日：2008-09-23

申请号：US11427457

申请日：2006-06-29

申请人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L21/20

CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

摘要翻译： 公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。 虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。 该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。 该方法消除了平面化的需要。

公开(公告)号：US20120133022A1

公开(公告)日：2012-05-31

申请号：US13359634

申请日：2012-01-27

申请人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L29/92 ,  H01L29/8605

CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

摘要翻译： 公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。 虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。 该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。 该方法消除了平面化的需要。

公开(公告)号：US20080224259A1

公开(公告)日：2008-09-18

申请号：US12106374

申请日：2008-04-21

申请人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L29/00 ,  H01L21/02

CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

公开(公告)号：US07394145B2

公开(公告)日：2008-07-01

申请号：US11928798

申请日：2007-10-30

申请人： Anil K Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L29/00 ,  H01L21/20

CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

摘要翻译： 公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。 虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。 该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在所述电介质层中形成通过所述介电层与所述无源元件的互连以及与所述虚拟无源元件的至少一部分重叠的虚拟互连部分。 该方法消除了平面化的需要。

公开(公告)号：US08487401B2

公开(公告)日：2013-07-16

申请号：US13359634

申请日：2012-01-27

申请人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L23/522

CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

摘要翻译： 公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。 虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。 该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。 该方法消除了平面化的需要。

公开(公告)号：US08119491B2

公开(公告)日：2012-02-21

申请号：US12106374

申请日：2008-04-21

申请人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L21/20

CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

摘要翻译： 公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。 虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。 该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。 该方法消除了平面化的需要。

公开(公告)号：US20080003759A1

公开(公告)日：2008-01-03

申请号：US11427457

申请日：2006-06-29

申请人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L21/20

CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

公开(公告)号：US20080173981A1

公开(公告)日：2008-07-24

申请号：US11624712

申请日：2007-01-19

申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L28/91 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An Integrated Circuit (IC) chip with one or more vertical plate capacitors, each vertical plate capacitor connected to circuits on the IC chip and a method of making the chip capacitors. The vertical plate capacitors are formed with base plate pattern (e.g., damascene copper) on a circuit layer and at least one upper plate layer (e.g., dual damascene copper) above, connected to and substantially identical with the base plate pattern. A vertical pair of capacitor plates are formed by the plate layer and base plate. Capacitor dielectric between the vertical pair of capacitor plates is, at least in part, a high-k dielectric.

摘要翻译： 具有一个或多个垂直板电容器的集成电路（IC）芯片，每个垂直板电容器连接到IC芯片上的电路和制造芯片电容器的方法。 垂直板电容器在电路层上形成有底板图案（例如，镶嵌铜），以及与基板图案连接并基本相同的至少一个上板层（例如双镶嵌铜）。 一对电容器板由板层和底板形成。 垂直对电容器板之间的电容电介质至少部分地是高k电介质。