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    Ensuring Transactional Ordering in I/O Agent
    3.
    发明申请
    Ensuring Transactional Ordering in I/O Agent 有权

    公开(公告)号：US20230064526A1

    公开(公告)日：2023-03-02

    申请号：US17657506

    申请日：2022-03-31

    Applicant: Apple Inc.

    Inventor： Sagi Lahav ,  Lital Levy - Rubin ,  Gaurav Garg ,  Gerard R. Williams, III ,  Samer Nassar ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan ,  Jeff Gonion

    IPC: G06F9/46 ,  G06F13/16

    Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include one or more queues and a transaction pipeline. The I/O agent circuit may issue, to the transaction pipeline from a queue of the one or more queues, a transaction of a series of transactions enqueued in a particular order. The I/O agent circuit may generate, at the transaction pipeline, a determination to return the transaction to the queue based on a detection of one or more conditions being satisfied. Based on the determination, the I/O agent circuit may reject, at the transaction pipeline, up to a threshold number of transactions that issued from the queue after the transaction issued. The I/O agent circuit may insert the transaction at a head of the queue such that the transaction is enqueued at the queue sequentially first for the series of transactions according to the particular order.

    DSB Operation with Excluded Region
    6.
    发明申请
    DSB Operation with Excluded Region 有权

    公开(公告)号：US20220083338A1

    公开(公告)日：2022-03-17

    申请号：US17469504

    申请日：2021-09-08

    Applicant: Apple Inc.

    Inventor： Jeff Gonion ,  John H. Kelm ,  James Vash ,  Pradeep Kanapathipillai ,  Mridul Agarwal ,  Gideon N. Levinsky ,  Richard F. Russo ,  Christopher M. Tsay

    IPC: G06F9/30 ,  G06F12/0875 ,  G06F12/02

    Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.

    Remote Cache Invalidation
    8.
    发明申请
    Remote Cache Invalidation 有权

    公开(公告)号：US20250103492A1

    公开(公告)日：2025-03-27

    申请号：US18582305

    申请日：2024-02-20

    Applicant: Apple Inc.

    Inventor： Brett S. Feero ,  Dennis R. Bradford ,  Gaurav Garg ,  Jeff Gonion ,  Bernard J. Semeria ,  James Vash ,  Richard F. Russo

    IPC: G06F12/0808 ,  G06F12/0882 ,  G06F12/1045

    Abstract: Techniques are disclosed relating to performing remote cache invalidations. In some embodiments, primary processor circuitry is configured to, based on execution of a remote invalidate instruction (e.g., an ISA-defined instruction), send a cache invalidate command to coprocessor circuitry. The coprocessor circuitry includes coprocessor cache circuitry and cache invalidation control circuitry configured to, in response to the cache invalidate command sent by the primary processor, invalidate one or more cache lines in the coprocessor cache circuitry without executing any instructions on the coprocessor circuitry.

    Pointer Authentication
    9.
    发明公开
    Pointer Authentication 审中-公开

    公开(公告)号：US20230421354A1

    公开(公告)日：2023-12-28

    申请号：US18326910

    申请日：2023-05-31

    Applicant: Apple Inc.

    Inventor： Yin Zin Mark Lam ,  Jeff Gonion

    IPC: H04L9/06 ,  H04L9/32

    CPC classification number: H04L9/0625 ,  H04L9/3247

    Abstract: In an embodiment, a processor includes hardware circuitry which may be used to detect that a return address has been modified since it was generated. In response to detecting the modification, the processor may be configured to signal an exception or otherwise initiate error handling to prevent execution at the modified return address. In an embodiment, the processor may perform a cryptographic signature operation on the return address to generate a signed return address, and the signature may be verified before the address is used as a return target.

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