公开(公告)号：US20160006018A1

公开(公告)日：2016-01-07

申请号：US14770441

申请日：2014-03-03

Applicant: APPLIED MATERIALS, INC.

Inventor： Fei WANG ,  Victor PEBENITO ,  Hooman BOLANDI ,  Connie P. WANG

IPC: H01M4/04 ,  H01M4/1391 ,  H01M4/1397 ,  H01M4/36

CPC classification number: H01M4/0471 ,  H01M4/0404 ,  H01M4/0419 ,  H01M4/13 ,  H01M4/139 ,  H01M4/1391 ,  H01M4/1397 ,  H01M4/366 ,  H01M10/0525 ,  H01M2004/021

Abstract: A method and apparatus for fabricating energy storage devices and device components is provided. It has been found that spraying of slurries comprising electro-active materials onto a flexible substrate and subsequently exposing the substrate to an increasing temperature gradient leads to the deposition of a dry or mostly dry film having reduced surface roughness. The increasing temperature gradient may result from a plurality of heated rollers over which the substrate traverses wherein each heated roller is heated to a temperature greater than the previous heated roller leading to the deposition of a dry or mostly dry film having a relatively smooth surface with low porosity. Deposition of a dry or mostly dry film eliminates the need for large and costly drying mechanism thus reducing both the cost and footprint of the apparatus.

Abstract translation: 提供了一种用于制造储能装置和装置部件的方法和装置。 已经发现，将包含电活性材料的浆料喷射到柔性基材上，随后将基材暴露于升高的温度梯度，导致沉积具有降低的表面粗糙度的干燥或大部分干燥的膜。 增加的温度梯度可以由多个加热的辊产生，多个加热的辊在基板上穿过，其中每个加热的辊被加热到比先前的加热辊大的温度，导致沉积具有相对平滑的表面的干或大多数干膜 孔隙度。 干燥或大多数干膜的沉积消除了对大型和昂贵的干燥机构的需要，从而降低了设备的成本和占地面积。

公开(公告)号：US20190237325A1

公开(公告)日：2019-08-01

申请号：US15880702

申请日：2018-01-26

Applicant: Applied Materials, Inc.

Inventor： Fei WANG ,  Miaojun WANG ,  Shishi JIANG ,  Pramit MANNA ,  Abhijit Basu MALLICK ,  Robert Jan VISSER

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/0273 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/31116 ,  H01L21/31138

Abstract: Embodiments described herein relate to methods for forming patterns of semiconductor devices utilizing parylene gapfill layers deposited using a thermal chemical vapor deposition (CVD) process. In one embodiment the patterns of semiconductor devices are formed by forming amorphous carbon (a-C) mandrels on first layers, depositing amorphous silicon (a-Si) layers over the a-C mandrels and the first layers, etching the a-Si spacer layers to expose top surfaces of the a-C mandrels and to expose the first layers, depositing parylene gapfill layers using the CVD process, removing portions of the parylene gapfill layers until the top surfaces are exposed; and removing the a-Si spacer layers to expose the first layers and form patterns of semiconductor devices having a-C mandrels and parylene mandrels.

公开(公告)号：US20190221422A1

公开(公告)日：2019-07-18

申请号：US16246776

申请日：2019-01-14

Applicant: Applied Materials, Inc.

Inventor： Fei WANG ,  Miaojun WANG ,  Pramit MANNA ,  Shishi JIANG ,  Abhijit Basu MALLICK ,  Robert Jan VISSER

IPC: H01L21/027

Abstract: Methods of selectively depositing a mask layer on a surface of a patterned substrate and self-aligned patterned masks are provided herein. In one embodiment, a method of selectivity depositing a mask layer includes positioning the patterned substrate on a substrate support in a processing volume of a processing chamber, exposing the surface of the patterned substrate to a parylene monomer gas, forming a first layer on the patterned substrate, wherein the first layer comprises a patterned parylene layer, and depositing a second layer on the first layer. In another embodiment, a self-aligned patterned mask comprises a parylene layer comprising a plurality of parylene features and a plurality of openings, the parylene layer is disposed on a patterned substrate comprising a dielectric layer and a plurality of metal features, the plurality of metal feature comprise a parylene deposition inhibitor metal, and the plurality of parylene features are selectivity formed on dielectric surfaces of the dielectric layer.

公开(公告)号：US20220310448A1

公开(公告)日：2022-09-29

申请号：US17839170

申请日：2022-06-13

Applicant: Applied Materials, Inc.

Inventor： Xin LIU ,  Fei WANG ,  Rui CHENG ,  Abhijit Basu MALLICK ,  Robert Jan VISSER

IPC: H01L21/768 ,  C23C16/01 ,  C23C16/24 ,  C23C16/455 ,  C23C16/46 ,  C23C16/56 ,  H01L21/02 ,  H01L21/3205

Abstract: Embodiments of the present disclosure relate to processes for filling trenches. The process includes depositing a first amorphous silicon layer on a surface of a layer and a second amorphous silicon layer in a portion of a trench formed in the layer, and portions of side walls of the trench are exposed. The first amorphous silicon layer is removed. The process further includes depositing a third amorphous silicon layer on the surface of the layer and a fourth amorphous silicon layer on the second amorphous silicon layer. The third amorphous silicon layer is removed. The deposition/removal cyclic processes may be repeated until the trench is filled with amorphous silicon layers. The amorphous silicon layers form a seamless amorphous silicon gap fill in the trench since the amorphous silicon layers are formed from bottom up.