公开(公告)号：US10043870B2

公开(公告)日：2018-08-07

申请号：US14918604

申请日：2015-10-21

Applicant: Applied Materials, Inc.

Inventor： Zhiyuan Ye ,  Xinyu Bao ,  Errol Antonio C. Sanchez ,  David K. Carlson ,  Keun-Yong Ban

IPC: H01L29/205 ,  H01L27/146 ,  H01L21/02

Abstract: Embodiments of the present disclosure generally relate to a film stack including layers of group III-V semiconductor materials. The film stack includes a phosphorous containing layer deposited over a silicon substrate, a GaAs containing layer deposited on the phosphorous containing layer, and an aluminum containing layer deposited on the GaAs containing layer. The GaAs containing layer between the phosphorous containing layer and the aluminum containing layer improves the surface smoothness of the aluminum containing layer.

公开(公告)号：US10125415B2

公开(公告)日：2018-11-13

申请号：US15668026

申请日：2017-08-03

Applicant: Applied Materials, Inc.

Inventor： Zhiyuan Ye ,  Errol Antonio C. Sanchez ,  Keun-Yong Ban ,  Xinyu Bao

IPC: H01L21/02 ,  C23C8/02

Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.

公开(公告)号：US09530888B2

公开(公告)日：2016-12-27

申请号：US15073245

申请日：2016-03-17

Applicant: Applied Materials, Inc.

Inventor： Keun-Yong Ban ,  Zhiyuan Ye ,  Errol Antonio C. Sanchez ,  Xinyu Bao ,  David K. Carlson

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/04 ,  H01L29/205 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/7849 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02439 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66522

Abstract: Embodiments of the present disclosure generally relate to a semiconductor device including layers of group III-V semiconductor materials. In one embodiment, the semiconductor device includes a phosphorous containing layer deposited on a silicon substrate, wherein a lattice mismatch between the phosphorous containing layer and the silicon substrate is less than 5%, a group III-V compound nucleation layer deposited on the phosphorous containing layer at a first temperature, the group III-V compound nucleation layer having a first thickness, a group III-V compound transition layer deposited on the group III-V compound nucleation layer at a second temperature higher than the first temperature, the group III-V compound transition layer having a second thickness larger than the first thickness, and the group III-V compound nucleation layer is different from the group III-V compound transition layer, and an active layer deposited on the group III-V compound transition layer.

Abstract translation: 本公开的实施例一般涉及包括III-V族III族半导体材料层的半导体器件。 在一个实施例中，半导体器件包括沉积在硅衬底上的含磷层，其中含磷层和硅衬底之间的晶格失配小于5％，III-V族化合物成核层沉积在含磷 III族化合物成核层，第III-V族化合物成核层，第III-V族化合物成核层，第III-V族化合物成核层，第III-V族化合物成核层， -V化合物过渡层，其具有大于第一厚度的第二厚度，III-V族化合物成核层与III-V族化合物过渡层不同，并且沉积在III-V族化合物过渡层上的活性层 。

公开(公告)号：US10043666B2

公开(公告)日：2018-08-07

申请号：US15055164

申请日：2016-02-26

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Errol Antonio C. Sanchez ,  Zhiyuan Ye ,  Keun-Yong Ban

IPC: H01L21/02 ,  H01L21/67 ,  C30B25/02

Abstract: Embodiments described herein generally relate to a substrate processing system, such as an etch processing system. In one embodiment, a method of processing a substrate is disclosed herein. The method includes removing a native oxide from a surface of the substrate, baking the substrate in a pre-treatment thermal chamber such that double atomic steps are formed on the surface of the substrate, and forming an epitaxial layer on the substrate after the substrate is baked.

公开(公告)号：US09752224B2

公开(公告)日：2017-09-05

申请号：US15210030

申请日：2016-07-14

Applicant: Applied Materials, Inc.

Inventor： Zhiyuan Ye ,  Errol Antonio C. Sanchez ,  Keun-Yong Ban ,  Xinyu Bao

IPC: H01L21/02 ,  C23C8/02

CPC classification number: C23C8/02 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262

Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.