公开(公告)号：US20220359723A1

公开(公告)日：2022-11-10

申请号：US17873380

申请日：2022-07-26

Applicant: Applied Materials, Inc.

Inventor： Sipeng Gu ,  Baonian Guo ,  Qintao Zhang ,  Wei Zou ,  Kyuha Shim

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/3215

Abstract: Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

公开(公告)号：US11955533B2

公开(公告)日：2024-04-09

申请号：US17873380

申请日：2022-07-26

Applicant: Applied Materials, Inc.

Inventor： Sipeng Gu ,  Baonian Guo ,  Qintao Zhang ,  Wei Zou ,  Kyuha Shim

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/28132 ,  H01L21/32155 ,  H01L29/66742 ,  H01L21/32139 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/78696

Abstract: Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

公开(公告)号：US12217974B2

公开(公告)日：2025-02-04

申请号：US17396101

申请日：2021-08-06

Applicant: Applied Materials, Inc.

Inventor： Sony Varghese ,  Pradeep Subrahmanyan ,  Dennis Rodier ,  Kyuha Shim

IPC: H01L21/3115 ,  H01J37/147 ,  H01J37/304 ,  H01J37/317 ,  H01L21/66

Abstract: Embodiments herein are directed to localized stress modulation by implanting a first side of a substrate to reduce in-plane distortion along a second side of the substrate. In some embodiments, a method may include providing a substrate, the substrate comprising a first main side opposite a second main side, wherein a plurality of features are disposed on the first main side, performing a metrology scan to the first main side to determine an amount of distortion to the substrate due to the formation of the plurality of features, and depositing a stress compensation film along the second main side of the substrate, wherein a stress and a thickness of the stress compensation film is determined based on the amount of distortion to the substrate. The method may further include directing ions to the stress compensation film in an ion implant procedure.

公开(公告)号：US11756796B2

公开(公告)日：2023-09-12

申请号：US17318843

申请日：2021-05-12

Applicant: Applied Materials, Inc.

Inventor： Rajesh Prasad ,  Martin Seamons ,  Shan Tang ,  Qi Gao ,  Deven Raj Mittal ,  Kyuha Shim

IPC: H01L21/02 ,  H01L21/3115 ,  H01L21/311

CPC classification number: H01L21/31155 ,  H01L21/0234 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02321 ,  H01L21/31116

Abstract: A method may include providing a substrate having, on a first surface of the substrate, a low dielectric constant layer characterized by a layer thickness. The method may include heating the substrate to a substrate temperature in a range of 200° C. to 550° C.; and directing an ion implant treatment to the low dielectric constant layer, while the substrate temperature is in the range of 200° C. to 550° C. As such, the ion implant treatment may include implanting a low weight ion species, at an ion energy generating an implant depth equal to 40% to 175% of the layer thickness.

公开(公告)号：US20220344171A1

公开(公告)日：2022-10-27

申请号：US17396101

申请日：2021-08-06

Applicant: Applied Materials, Inc.

Inventor： Sony Varghese ,  Pradeep Subrahmanyan ,  Dennis Rodier ,  Kyuha Shim

IPC: H01L21/3115 ,  H01L21/66 ,  H01J37/317 ,  H01J37/304 ,  H01J37/147

Abstract: Embodiments herein are directed to localized stress modulation by implanting a first side of a substrate to reduce in-plane distortion along a second side of the substrate. In some embodiments, a method may include providing a substrate, the substrate comprising a first main side opposite a second main side, wherein a plurality of features are disposed on the first main side, performing a metrology scan to the first main side to determine an amount of distortion to the substrate due to the formation of the plurality of features, and depositing a stress compensation film along the second main side of the substrate, wherein a stress and a thickness of the stress compensation film is determined based on the amount of distortion to the substrate. The method may further include directing ions to the stress compensation film in an ion implant procedure.

公开(公告)号：US20230268188A1

公开(公告)日：2023-08-24

申请号：US17703254

申请日：2022-03-24

Applicant: Applied Materials, Inc.

Inventor： Sungho Jo ,  Rajesh Prasad ,  Kyuha Shim

IPC: H01L21/308 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L21/3086 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/26533 ,  H01L21/3081

Abstract: Methods of forming a silicon hardmask are disclosed. In one example, a method may include forming a silicon mask over a device layer, forming a carbon mask over the silicon mask, and forming an opening through the carbon mask. The method may further include forming an oxide layer within the opening by performing an ion implantation process to an upper surface of the silicon mask.

公开(公告)号：US20220367205A1

公开(公告)日：2022-11-17

申请号：US17318843

申请日：2021-05-12

Applicant: Applied Materials, Inc.

Inventor： Rajesh Prasad ,  Martin Seamons ,  Shan Tang ,  Qi Gao ,  Deven Raj Mittal ,  Kyuha Shim

IPC: H01L21/3115 ,  H01L21/02

Abstract: A method may include providing a substrate having, on a first surface of the substrate, a low dielectric constant layer characterized by a layer thickness. The method may include heating the substrate to a substrate temperature in a range of 200° C. to 550° C.; and directing an ion implant treatment to the low dielectric constant layer, while the substrate temperature is in the range of 200° C. to 550° C. As such, the ion implant treatment may include implanting a low weight ion species, at an ion energy generating an implant depth equal to 40% to 175% of the layer thickness.

公开(公告)号：US11430877B2

公开(公告)日：2022-08-30

申请号：US17098082

申请日：2020-11-13

Applicant: Applied Materials, Inc.

Inventor： Sipeng Gu ,  Baonian Guo ,  Qintao Zhang ,  Wei Zou ,  Kyuha Shim

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/3215 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

公开(公告)号：US20220157968A1

公开(公告)日：2022-05-19

申请号：US17098082

申请日：2020-11-13

Applicant: Applied Materials, Inc.

Inventor： Sipeng Gu ,  Baonian Guo ,  Qintao Zhang ,  Wei Zou ,  Kyuha Shim

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/3215

Abstract: Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.