公开(公告)号：US20190385825A1

公开(公告)日：2019-12-19

申请号：US16418274

申请日：2019-05-21

Applicant: Applied Materials, Inc.

Inventor： Jian WU ,  Wei LIU ,  Theresa Kramer GUARINI ,  Linlin WANG ,  Malcolm BEVAN ,  Lara HAWRYLCHAK

IPC: H01J37/32 ,  C23C26/00

Abstract: Embodiments described herein generally relate to a method and apparatus for fabricating a chamber component for a plasma process chamber. In one embodiment a chamber component used within a plasma processing chamber is provided that includes a metallic base material comprising a roughened non-planar first surface, wherein the roughened non-planar surface has an Ra surface roughness of between 4 micro-inches and 80 micro-inches, a planar silica coating formed over the roughened non-planar surface, wherein the planar silica coating has a surface that has an Ra surface roughness that is less than the Ra surface roughness of the roughened non-planar surface, a thickness between about 0.2 microns and about 10 microns, less than 1% porosity by volume, and contains less than 2E12 atoms/centimeters2 of aluminum.

公开(公告)号：US20170294320A1

公开(公告)日：2017-10-12

申请号：US15484527

申请日：2017-04-11

Applicant: Applied Materials, Inc.

Inventor： Zhenjiang CUI ,  Xing ZHONG ,  Jie LIU ,  Linlin WANG

IPC: H01L21/3213 ,  H01L29/51 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/32136 ,  H01J37/32357 ,  H01J37/32422 ,  H01L21/02071 ,  H01L21/28088 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66795

Abstract: A method for processing a semiconductor substrate is described herein. The method described herein includes generating fluorine radicals and ions, delivering the fluorine radicals through an ion blocker to a processing region, and removing one or more portions of a gate structure to expose one or more portions of a gate dielectric material disposed thereunder. The gate structure includes at least two ceramic or metal layers, and the gate dielectric material is made of a high-k dielectric material. A substrate having the gate structure and gate dielectric material formed thereon is disposed in the processing region, and the temperature of the substrate is maintained at about 60 degrees Celsius or higher. By etching the gate structure using fluorine radicals at a temperature greater or equal to 60 degrees Celsius, the at least two ceramic or metal layers have a flat cross sectional profile.

公开(公告)号：US20170236702A1

公开(公告)日：2017-08-17

申请号：US15413167

申请日：2017-01-23

Applicant: Applied Materials, Inc.

Inventor： Johanes S. SWENBERG ,  Linlin WANG ,  Wei LIU

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L21/0228 ,  H01L21/02181 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/518

Abstract: Embodiments of the present disclosure generally relate to methods for forming a high-k gate dielectric in a transistor. The high-k gate dielectric may be formed by introducing a fluorine containing gas into a processing chamber during the deposition of the high-k gate dielectric in the processing chamber. In one embodiment, the high-k gate dielectric is formed by an ALD process in a processing chamber, and a fluorine containing gas is introduced into the processing chamber during one or more stages of the ALD process. Fluorine ions, molecules or radicals from the fluorine containing gas (may be activated by a plasma) can fill the oxygen vacancies in the high-k dielectric.

公开(公告)号：US20230245863A1

公开(公告)日：2023-08-03

申请号：US18131306

申请日：2023-04-05

Applicant: Applied Materials, Inc.

Inventor： Jian WU ,  Wei LIU ,  Theresa Kramer GUARINI ,  Linlin WANG ,  Malcolm BEVAN ,  Lara HAWRYLCHAK

IPC: H01J37/32 ,  C23C26/00

CPC classification number: H01J37/32495 ,  C23C26/00 ,  H01J37/32477

Abstract: Embodiments described herein generally relate to a method and apparatus for fabricating a chamber component for a plasma process chamber. In one embodiment a chamber component used within a plasma processing chamber is provided that includes a metallic base material comprising a roughened non-planar first surface, wherein the roughened non-planar surface has an Ra surface roughness of between 4 micro-inches and 80 micro-inches, a planar silica coating formed over the roughened non-planar surface, wherein the planar silica coating has a surface that has an Ra surface roughness that is less than the Ra surface roughness of the roughened non-planar surface, a thickness between about 0.2 microns and about 10 microns, less than 1% porosity by volume, and contains less than 2E12 atoms/centimeters2 of aluminum.

公开(公告)号：US20180033619A1

公开(公告)日：2018-02-01

申请号：US15417473

申请日：2017-01-27

Applicant: Applied Materials, Inc.

Inventor： Wei LIU ,  Linlin WANG

IPC: H01L21/02 ,  H01L21/28

CPC classification number: H01L21/02321 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3105 ,  H01L29/517 ,  H01L29/518

Abstract: Embodiments of the present disclosure generally relate to methods for forming a dielectric material on a substrate, and more specifically, to methods for forming a high-k dielectric layer in an electronic device. In one embodiment, the method includes depositing a high-k dielectric layer on a substrate and fluorinating the deposited high-k dielectric layer. The fluorinating the high-k dielectric layer includes exposing the high-k dielectric layer to a fluorine containing plasma at temperature between about 200 degrees Celsius and about 550 degrees Celsius. At this temperature range, the fluorine radicals form fluorine bonds at the interface between the high-k dielectric layer and the substrate without etching any materials.