公开(公告)号：US20230288916A1

公开(公告)日：2023-09-14

申请号：US17692671

申请日：2022-03-11

Applicant: Applied Materials, Inc.

Inventor： Ying WANG ,  Xundong DAI ,  Guan Huei SEE ,  Ruiping WANG ,  Michael R. RICE ,  Hari Kishen PONNEKANTI ,  Nirmalya MAITY

IPC: G05B19/418 ,  H01L21/687 ,  H01L21/67

CPC classification number: G05B19/418 ,  H01L21/67121 ,  H01L21/68771 ,  H01L21/68778 ,  G05B2219/45031

Abstract: Apparatus for extending substrate queue time for hybrid bonding by preserving plasma activation. In some embodiments, the apparatus may include an environmentally controllable space with a support for holding a die or a substrate, a gas velocity accelerator that recirculates one or more gases laterally across the support, a filter, a humidifier apparatus that is fluidly connected to the environmentally controllable space, wherein the humidifier apparatus enables controllable humidity levels within the environmentally controllable space, a pressurizing apparatus fluidly connected to the humidifier apparatus on an output and fluidly connected to at least one gas supply on an input, a relative humidity (RH) sensor positioned within the environmentally controllable space, and an environment controller in communication with at least the humidifier apparatus and the RH sensor, wherein the environment controller is configured to maintain an RH level of approximately 80% to approximately 95%.

公开(公告)号：US20240387458A1

公开(公告)日：2024-11-21

申请号：US18199183

申请日：2023-05-18

Applicant: Applied Materials, Inc.

Inventor： Suketu PARIKH ,  Andrew YEOH ,  Arvind SUNDARRAJAN ,  Nirmalya MAITY ,  Balasubramanian PRANATHARTHIHARAN ,  Martinus Maria BERKENS

IPC: H01L25/065 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/367 ,  H01L23/522 ,  H01L25/00

Abstract: In some embodiments, a method for forming a multiple die stack comprises forming a first circuit wafer with multiple first circuit dies and a first circuit support layer on a bottom of the first circuit wafer where each first circuit die has a power and circuit layer underlying a power and signal layer, forming an interposer wafer with multiple interposer dies and an interposer support layer on a top of the interposer wafer where each interposer die has a power and signal layer underlying a power via and signal via layer, and hybrid bonding a top surface of the first circuit wafer to a bottom surface of the interposer wafer to form a first bonded wafer with electrical power and signal connections between the multiple first circuit dies and the multiple interposer dies where the interposer wafer provides structural support of the first bonded wafer during subsequent processing.

公开(公告)号：US20230187222A1

公开(公告)日：2023-06-15

申请号：US17549325

申请日：2021-12-13

Applicant: Applied Materials, Inc.

Inventor： Mukhles SOWWAN ,  Samer BANNA ,  Nirmalya MAITY ,  Nalamasu OMKARAM ,  Gary E. DICKERSON

IPC: H01L21/48 ,  H01L23/14 ,  H01L23/498

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L23/147 ,  H01L23/49822

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, printed circuit board (PCB) assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a substrate core (e.g., a core structure) is implanted with dopants to achieve a desired bulk resistivity or conductivity. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.