公开(公告)号：US10259007B2

公开(公告)日：2019-04-16

申请号：US14716489

申请日：2015-05-19

Applicant: Applied Materials, Inc.

Inventor： Kurtis Leschkies ,  Steven Verhaverbeke ,  Robert Visser

IPC: B05B5/04 ,  B05B1/00 ,  D01D5/00 ,  D01D11/06 ,  D01F1/09 ,  D01F6/50 ,  B05D1/00 ,  B22F9/08

Abstract: Embodiments of the invention generally include apparatus and methods for depositing nanowires in a predetermined pattern during an electrospinning process. An apparatus includes a nozzle for containing and ejecting a deposition material, and a voltage source coupled to the nozzle to eject the deposition material. One or more electric field shaping devices are positioned to shape the electric field adjacent to a substrate to control the trajectory of the ejected deposition material. The electric field shaping device converges an electric field at a point near the surface of the substrate to accurately deposit the deposition material on the substrate in a predetermined pattern. The methods include applying a voltage to a nozzle to eject an electrically-charged deposition material towards a substrate, and shaping one or more electric fields to control the trajectory of the electrically-charged deposition material. The deposition material is then deposited on the substrate in a predetermined pattern.

公开(公告)号：US08895351B2

公开(公告)日：2014-11-25

申请号：US13656485

申请日：2012-10-19

Applicant: Applied Materials, Inc.

Inventor： Kurtis Leschkies ,  Steven Verhaverbeke ,  Robert Visser

IPC: H01L21/00 ,  H01L31/0392 ,  H01L31/0224

CPC classification number: H01L31/022425 ,  H01L31/03921 ,  Y02E10/50

Abstract: The present invention generally includes an apparatus and process of forming a conductive layer on a surface of a host substrate, which can be directly used to form a portion of an electronic device. More specifically, one or more of the embodiments disclosed herein include a process of forming a conductive layer on a surface of a substrate using an electrospinning type deposition process. Embodiments of the conductive layer forming process described herein can be used to reduce the number of processing steps required to form the conductive layer, improve the electrical properties of the formed conductive layer and reduce the conductive layer formation process complexity over current state-of-the-art conductive layer formation techniques. Typical electronic device formation processes that can benefit from one or more of the embodiments described herein include, but are not limited to processes used to form solar cells, electronic visual display devices and touchscreen type technologies.

Abstract translation: 本发明通常包括在主基板的表面上形成导电层的装置和工艺，其可以直接用于形成电子器件的一部分。 更具体地，本文公开的一个或多个实施例包括使用静电纺丝型沉积工艺在基板的表面上形成导电层的工艺。 本文所述的导电层形成方法的实施方案可用于减少形成导电层所需的处理步骤的数量，改善所形成的导电层的电性能，并降低导电层形成工艺的复杂性，超过目前的状态 - 导电层形成技术。 可以受益于本文所述的一个或多个实施方案的典型电子器件形成方法包括但不限于用于形成太阳能电池的方法，电子视觉显示装置和触摸屏型技术。

公开(公告)号：US09385239B2

公开(公告)日：2016-07-05

申请号：US14203433

申请日：2014-03-10

Applicant: Applied Materials, Inc.

Inventor： Kurtis Leschkies ,  Steven Verhaverbeke ,  Robert Visser ,  John M. White ,  Yan Ye ,  Dong-Kil Yim

IPC: H01L29/786 ,  H01L29/49

CPC classification number: H01L29/7869 ,  H01L29/4908

Abstract: The present invention generally relates to a thin film semiconductor device having a buffer layer formed between the semiconductor layer and one or more layers. In one embodiment, a thin film semiconductor device includes a semiconductor layer having a first work function and a first electron affinity level, a buffer layer having a second work function greater than the first work function and a second electron affinity level that is less than the first electron affinity level; and a gate dielectric layer having a third work function less than the second work function and a third electron affinity level that is greater than the second electron affinity level.

Abstract translation: 本发明一般涉及一种在半导体层与一层或多层之间形成缓冲层的薄膜半导体器件。 在一个实施例中，薄膜半导体器件包括具有第一功函数和第一电子亲和度的半导体层，具有大于第一功函数的第二功函数的缓冲层和小于第一功函数的第二电子亲和度 第一电子亲和力水平; 以及具有小于第二功函数的第三功函数和大于第二电子亲和度的第三电子亲和度的栅介质层。