公开(公告)号：US09634039B2

公开(公告)日：2017-04-25

申请号：US15202070

申请日：2016-07-05

Applicant: Applied Materials, Inc.

Inventor： Soo Young Choi ,  Tae Kyung Won ,  Dong-Kil Yim ,  Yi Cui ,  Xuena Zhang

IPC: H01L51/52 ,  H01L27/12 ,  H01L27/32

CPC classification number: H01L27/1248 ,  H01L27/3262

Abstract: Embodiments of the present disclosure generally relate to methods and devices for use of low temperature polysilicon (LTPS) thin film transistors in liquid crystal display (LCD) and organic light-emitting diode (OLED) displays.

公开(公告)号：US10224432B2

公开(公告)日：2019-03-05

申请号：US15456418

申请日：2017-03-10

Applicant: Applied Materials, Inc.

Inventor： Rodney Shunleong Lim ,  Dong-Kil Yim

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/223 ,  H01L21/423 ,  H01L29/20 ,  H01L29/207 ,  H01L29/24 ,  H01L29/49 ,  H01L29/66

Abstract: Embodiments of the disclosure generally provide methods of forming thin film transistor (TFT) device structure with good interface management between active layers of a metal electrode layer and/or source/drain electrode layers and a nearby insulating material so as to provide high electrical performance devices, or for other suitable display applications. In one embodiment, a thin film transistor structure includes a contact region formed between fluorine-doped source and drain regions disposed on a substrate, a gate insulating layer disposed on the contact region, and a metal electrode layer disposed on the gate insulator layer.

公开(公告)号：US12076763B2

公开(公告)日：2024-09-03

申请号：US16007876

申请日：2018-06-13

Applicant: Applied Materials, Inc.

Inventor： Yujia Zhai ,  Lai Zhao ,  Xiangxin Rui ,  Dong-Kil Yim ,  Tae Kyung Won ,  Soo Young Choi

IPC: B08B7/00 ,  B08B9/00 ,  C23C16/44 ,  H01J37/32 ,  H01L21/02 ,  H01L21/687 ,  H01L27/12 ,  H01L29/49 ,  H01L49/02

CPC classification number: B08B7/0035 ,  B08B9/00 ,  C23C16/4405 ,  H01J37/32082 ,  H01L27/1255 ,  H01L29/4908 ,  H01J2237/335 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/68742 ,  H01L28/40

Abstract: In one implementation, a method for cleaning a processing chamber is provided. The method comprises introducing a reactive species into a processing chamber having a residual high-k dielectric material formed on one or more interior surfaces of the processing chamber. The reactive species is formed from a halogen-containing gas mixture and the one or more interior surfaces include at least one surface having a coating material formed thereon. The method further comprises reacting the residual high-k dielectric material with the reactive species to form a volatile product. The method further comprises removing the volatile product from the processing chamber. The removal rate of the residual high-k dielectric material is greater than a removal rate of the coating material. The high-k dielectric material is selected from zirconium dioxide (ZrO2) and hafnium dioxide (HfO2). The coating material includes a compound selected from alumina (Al2O3), yttrium-containing compounds, and combinations thereof.

公开(公告)号：US10854737B2

公开(公告)日：2020-12-01

申请号：US15874081

申请日：2018-01-18

Applicant: Applied Materials, Inc.

Inventor： Soo Young Choi ,  Beom Soo Park ,  Yi Cui ,  Tae Kyung Won ,  Dong-Kil Yim

IPC: H01L23/31 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786

Abstract: Techniques are disclosed for methods of post-treating an etch stop or a passivation layer in a thin film transistor to increase the stability behavior of the thin film transistor.

公开(公告)号：US10134878B2

公开(公告)日：2018-11-20

申请号：US15359325

申请日：2016-11-22

Applicant: Applied Materials, Inc.

Inventor： Hao-Chien Hsu ,  Dong-Kil Yim ,  Tae Kyung Won ,  Xuena Zhang ,  Won Ho Sung ,  Rodney Shunleong Lim

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02

Abstract: Embodiments of the present disclosure generally relate to methods for forming a TFT having a metal oxide layer. The method may include forming a metal oxide layer and treating the metal oxide layer with a fluorine containing gas or plasma. The fluorine treatment of the metal oxide layer helps fill the oxygen vacancies in the metal oxide channel layer, leading to a more stable TFT and preventing a negative threshold voltage in the TFT.

公开(公告)号：US10381454B2

公开(公告)日：2019-08-13

申请号：US15411724

申请日：2017-01-20

Applicant: Applied Materials, Inc.

Inventor： Xuena Zhang ,  Dong-Kil Yim ,  Wenqing Dai ,  Harvey You ,  Tae Kyung Won ,  Hsiao-Lin Yang ,  Wan-Yu Lin ,  Yun-chu Tsai

IPC: H01L21/02 ,  H01L27/12 ,  H01L27/32 ,  H01L29/49 ,  H01L49/02 ,  G02F1/1362 ,  G02F1/1368

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor with high capacitance and low leakage as well as a good interface control for thin film transistor (TFT) applications. In one embodiment, a thin film transistor structure includes a capacitor formed in a thin film transistor device. The capacitor further includes a common electrode disposed on a substrate, a dielectric layer formed on the common electrode and a pixel electrode formed on the dielectric layer. An interface protection layer formed between the common electrode and the dielectric layer, or between the dielectric layer and the pixel electrode. A gate insulating layer fabricated by a high-k material may also be utilized in the thin film transistor structure.

公开(公告)号：US09385239B2

公开(公告)日：2016-07-05

申请号：US14203433

申请日：2014-03-10

Applicant: Applied Materials, Inc.

Inventor： Kurtis Leschkies ,  Steven Verhaverbeke ,  Robert Visser ,  John M. White ,  Yan Ye ,  Dong-Kil Yim

IPC: H01L29/786 ,  H01L29/49

CPC classification number: H01L29/7869 ,  H01L29/4908

Abstract: The present invention generally relates to a thin film semiconductor device having a buffer layer formed between the semiconductor layer and one or more layers. In one embodiment, a thin film semiconductor device includes a semiconductor layer having a first work function and a first electron affinity level, a buffer layer having a second work function greater than the first work function and a second electron affinity level that is less than the first electron affinity level; and a gate dielectric layer having a third work function less than the second work function and a third electron affinity level that is greater than the second electron affinity level.

Abstract translation: 本发明一般涉及一种在半导体层与一层或多层之间形成缓冲层的薄膜半导体器件。 在一个实施例中，薄膜半导体器件包括具有第一功函数和第一电子亲和度的半导体层，具有大于第一功函数的第二功函数的缓冲层和小于第一功函数的第二电子亲和度 第一电子亲和力水平; 以及具有小于第二功函数的第三功函数和大于第二电子亲和度的第三电子亲和度的栅介质层。

公开(公告)号：US12237406B2

公开(公告)日：2025-02-25

申请号：US17082570

申请日：2020-10-28

Applicant: Applied Materials, Inc.

Inventor： Soo Young Choi ,  Beom Soo Park ,  Yi Cui ,  Tae Kyung Won ,  Dong-Kil Yim

IPC: H01L29/786 ,  H01L21/02 ,  H01L23/31 ,  H01L29/66

Abstract: Techniques are disclosed for methods of post-treating an etch stop or a passivation layer in a thin film transistor to increase the stability behavior of the thin film transistor.

公开(公告)号：US11101338B2

公开(公告)日：2021-08-24

申请号：US16243314

申请日：2019-01-09

Applicant: Applied Materials, Inc.

Inventor： Jung Bae Kim ,  Dong-Kil Yim ,  Soo Young Choi ,  Lai Zhao

IPC: H01L27/32 ,  H01L27/12 ,  G09G3/3233

Abstract: Disclosed herein is a sub-pixel circuit for a display device. The sub-pixel circuit has a driving TFT and at least one switching TFT. The at least one switching TFT is an oxide TFT. The sub-pixel circuit additionally has at least one storage capacitor wherein the storage capacitor has a capacitance between about 1 fF and about 55 fF.

公开(公告)号：US09935183B2

公开(公告)日：2018-04-03

申请号：US15412545

申请日：2017-01-23

Applicant: Applied Materials, Inc.

Inventor： Dong-Kil Yim ,  Tae Kyung Won ,  Seon-Mee Cho ,  John M. White

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/786 ,  H01L29/24 ,  H01L21/467

CPC classification number: H01L29/66969 ,  H01L21/467 ,  H01L29/24 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/7869

Abstract: The present invention generally relates to TFTs and methods for fabricating TFTs. For either back channel etch TFTs or for etch stop TFTs, multiple layers for the passivation layer or the etch stop layers permits a very dense capping layer to be formed over a less dense back channel protection layer. The capping layer can be sufficiently dense so that few pin holes are present and thus, hydrogen may not pass through to the semiconductor layer. As such, hydrogen containing precursors may be used for the capping layer deposition.