公开(公告)号：US10790183B2

公开(公告)日：2020-09-29

申请号：US16407510

申请日：2019-05-09

申请人： Applied Materials, Inc.

发明人： Shiyu Sun ,  Keith Tatseun Wong ,  Kurtis Leschkies ,  Namsung Kim ,  Srinivas Nemani

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L21/324 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L29/06

摘要： Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure is oxidized by a high pressure oxidation process to form a buried oxide layer adjacent the substrate.

公开(公告)号：US20190228982A1

公开(公告)日：2019-07-25

申请号：US16246711

申请日：2019-01-14

申请人： Applied Materials, Inc.

发明人： Yihong Chen ,  Rui Cheng ,  Pramit Manna ,  Abhijit Basu Mallick ,  Shishi Jiang ,  Yong Wu ,  Kurtis Leschkies ,  Srinivas Gandikota

IPC分类号： H01L21/3105 ,  C23C16/56 ,  H01L21/02

摘要： Aspects of the disclosure include methods of processing a substrate. The method includes depositing a conformal layer on a substrate which contains seams. The substrate is treated using a high pressure anneal in the presence of an oxidizer.

公开(公告)号：US10283344B2

公开(公告)日：2019-05-07

申请号：US15325419

申请日：2015-07-10

申请人： Applied Materials, Inc.

发明人： Steven Verhaverbeke ,  Han-Wen Chen ,  Roman Gouk ,  Kurtis Leschkies

IPC分类号： H01J37/32 ,  H01L21/02 ,  H01L21/67

摘要： The present disclosure generally relates to apparatus and methods for forming a low-k dielectric material on a substrate. The method includes various substrate processing steps utilizing a wet processing chamber, a solvent exchange chamber, and a supercritical fluid chamber. More specifically, a dielectric material in an aqueous solution may be deposited on the substrate and a solvent exchange process may be performed to prepare the substrate for a supercritical drying process. During the supercritical drying process, liquids present in the solution and remaining on the substrate from the solvent exchange process are removed via sublimation during the supercritical drying process. The resulting dielectric material formed on the substrate may be considered a silica aerogel which exhibits a very low k-value.

公开(公告)号：US10096516B1

公开(公告)日：2018-10-09

申请号：US15681320

申请日：2017-08-18

申请人： Applied Materials, Inc.

发明人： Kurtis Leschkies ,  Steven Verhaverbeke

IPC分类号： H01L21/768 ,  H01L21/02

摘要： Embodiments of the disclosure generally relate to a method of improving quality of a barrier layer suitable for forming high aspect ratio through substrate vias. In one example, a method for depositing a barrier layer includes depositing a barrier layer in a hole formed in a substrate, exposing the deposited barrier layer to a processing gas at a pressure greater than about 2 bars, and, maintaining a temperature of the substrate between about 150 degrees and about 700 degrees Celsius while in the presence of the processing gas.

公开(公告)号：US11862546B2

公开(公告)日：2024-01-02

申请号：US16698680

申请日：2019-11-27

申请人： Applied Materials, Inc.

发明人： Han-Wen Chen ,  Steven Verhaverbeke ,  Giback Park ,  Kyuil Cho ,  Kurtis Leschkies ,  Roman Gouk ,  Chintan Buch ,  Vincent Dicaprio

IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L23/14

CPC分类号： H01L23/49838 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49866

摘要： The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

公开(公告)号：US11694912B2

公开(公告)日：2023-07-04

申请号：US17329948

申请日：2021-05-25

申请人： Applied Materials, Inc.

发明人： Jean Delmas ,  Steven Verhaverbeke ,  Kurtis Leschkies

IPC分类号： H01L21/67 ,  F27B9/36 ,  H01L21/677 ,  H01L21/324

CPC分类号： H01L21/67109 ,  F27B9/36 ,  H01L21/324 ,  H01L21/67017 ,  H01L21/6719 ,  H01L21/67248 ,  H01L21/67754 ,  H01L21/67748

摘要： Embodiments of the disclosure relate to an apparatus and method for annealing one or more semiconductor substrates. In one embodiment, a processing chamber is disclosed. The processing chamber includes a chamber body enclosing an internal volume, a substrate support disposed in the internal volume and configured to support a substrate during processing, a gas panel configured to provide a processing fluid into the internal volume, and a temperature-controlled fluid circuit configured to maintain the processing fluid at a temperature above a condensation point of the processing fluid. The temperature-controlled fluid circuit includes a gas conduit fluidly coupled to a port on the chamber body at a first end and to the gas panel at a second end.

公开(公告)号：US11232951B1

公开(公告)日：2022-01-25

申请号：US16928252

申请日：2020-07-14

申请人： Applied Materials, Inc.

发明人： Wei-Sheng Lei ,  Kurtis Leschkies ,  Roman Gouk ,  Steven Verhaverbeke ,  Visweswaren Sivaramakrishnan

IPC分类号： H01L21/268 ,  H01L21/768 ,  B23K26/386 ,  H01L21/68 ,  B23K26/00 ,  H01L21/67

摘要： In an embodiment is provided a method of forming a blind via in a substrate comprising a mask layer, a conductive layer, and a dielectric layer that includes conveying the substrate to a scanning chamber; determining one or more properties of the blind via, the one or more properties comprising a top diameter, a bottom diameter, a volume, or a taper angle of about 80° or more; focusing a laser beam at the substrate to remove at least a portion of the mask layer; adjusting the laser process parameters based on the one or more properties; and focusing the laser beam, under the adjusted laser process parameters, to remove at least a portion of the dielectric layer within the volume to form the blind via. In some embodiments, the mask layer can be pre-etched. In another embodiment is provided an apparatus for forming a blind via in a substrate.

公开(公告)号：US11018032B2

公开(公告)日：2021-05-25

申请号：US16378140

申请日：2019-04-08

申请人： Applied Materials, Inc.

发明人： Jean Delmas ,  Steven Verhaverbeke ,  Kurtis Leschkies

IPC分类号： H01L21/67 ,  H01L21/677 ,  F27B9/36 ,  H01L21/324

摘要： Embodiments of the disclosure relate to an apparatus and method for annealing one or more semiconductor substrates. In one embodiment, a processing chamber is disclosed. The processing chamber includes a chamber body enclosing an internal volume, a substrate support disposed in the internal volume and configured to support a substrate during processing, a gas panel configured to provide a processing fluid into the internal volume, and a temperature-controlled fluid circuit configured to maintain the processing fluid at a temperature above a condensation point of the processing fluid. The temperature-controlled fluid circuit includes a gas conduit fluidly coupled to a port on the chamber body at a first end and to the gas panel at a second end.

公开(公告)号：US10937726B1

公开(公告)日：2021-03-02

申请号：US16746681

申请日：2020-01-17

申请人： Applied Materials, Inc.

发明人： Han-Wen Chen ,  Steven Verhaverbeke ,  Giback Park ,  Kyuil Cho ,  Kurtis Leschkies ,  Roman Gouk ,  Chintan Buch ,  Vincent DiCaprio

IPC分类号： H01L23/498 ,  H01L23/14 ,  H01L21/48

摘要： The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

公开(公告)号：US09935005B2

公开(公告)日：2018-04-03

申请号：US15347948

申请日：2016-11-10

申请人： Applied Materials, Inc.

发明人： Kurtis Leschkies ,  Steven Verhaverbeke

IPC分类号： H01L21/31 ,  H01L29/06 ,  H01L21/30 ,  H01L21/768 ,  C23C16/455 ,  C23C16/48 ,  C23C16/50 ,  C23C16/52 ,  C23C16/56 ,  H01L21/67 ,  C23C16/02 ,  C23C16/04

CPC分类号： H01L21/76879 ,  C23C16/02 ,  C23C16/045 ,  C23C16/45527 ,  C23C16/45536 ,  C23C16/45544 ,  C23C16/482 ,  C23C16/50 ,  C23C16/52 ,  C23C16/56 ,  H01L21/67075 ,  H01L21/76802 ,  H01L21/76883

摘要： A method of device processing. The method may include providing a cavity in a layer, directing energetic flux to a bottom surface of the cavity, performing an exposure of the cavity to a moisture-containing ambient, and introducing a fill material in the cavity using an atomic layer deposition (ALD) process, wherein the fill material is selectively deposited on the bottom surface of the cavity with respect to a sidewall of the cavity.