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    RF choke for gas delivery to an RF driven electrode in a plasma processing apparatus
    2.
    发明授权
    RF choke for gas delivery to an RF driven electrode in a plasma processing apparatus 有权

    公开(公告)号：US10304607B2

    公开(公告)日：2019-05-28

    申请号：US15668064

    申请日：2017-08-03

    Applicant: Applied Materials, Inc.

    Inventor： Jozef Kudela ,  Carl A. Sorensen ,  John M. White

    IPC: H05H1/46 ,  H01F17/06 ,  C23C16/455 ,  H01J37/32 ,  C23C16/505 ,  H01F27/08

    Abstract: In large area plasma processing systems, process gases may be introduced to the chamber via the showerhead assembly which may be driven as an RF electrode. The gas feed tube, which is grounded, is electrically isolated from the showerhead. The gas feed tube may provide not only process gases, but also cleaning gases from a remote plasma source to the process chamber. The inside of the gas feed tube may remain at either a low RF field or a zero RF field to avoid premature gas breakdown within the gas feed tube that may lead to parasitic plasma formation between the gas source and the showerhead. By feeding the gas through an RF choke, the RF field and the processing gas may be introduced to the processing chamber through a common location and thus simplify the chamber design.

    Plasma uniformity control by gas diffuser hole design
    3.
    发明授权
    Plasma uniformity control by gas diffuser hole design 有权

    公开(公告)号：US10262837B2

    公开(公告)日：2019-04-16

    申请号：US14932618

    申请日：2015-11-04

    Applicant: Applied Materials, Inc.

    Inventor： Soo Young Choi ,  John M. White ,  Qunhua Wang ,  Li Hou ,  Ki Woon Kim ,  Shinichi Kurita ,  Tae Kyung Won ,  Suhail Anwar ,  Beom Soo Park ,  Robin L. Tiner

    IPC: H01J37/32 ,  C23C16/34 ,  C23C16/455 ,  C23C16/509

    Abstract: Embodiments of a gas diffuser plate for distributing gas in a processing chamber are provided. The gas distribution plate includes a diffuser plate having an upstream side and a downstream side, and a plurality of gas passages passing between the upstream and downstream sides of the diffuser plate. The gas passages include hollow cathode cavities at the downstream side to enhance plasma ionization. The depths, the diameters, the surface area and density of hollow cathode cavities of the gas passages that extend to the downstream end can be gradually increased from the center to the edge of the diffuser plate to improve the film thickness and property uniformity across the substrate. The increasing diameters, depths and surface areas from the center to the edge of the diffuser plate can be created by bending the diffuser plate toward downstream side, followed by machining out the convex downstream side. Bending the diffuser plate can be accomplished by a thermal process or a vacuum process. The increasing diameters, depths and surface areas from the center to the edge of the diffuser plate can also be created computer numerically controlled machining. Diffuser plates with gradually increasing diameters, depths and surface areas of the hollow cathode cavities from the center to the edge of the diffuser plate have been shown to produce improved uniformities of film thickness and film properties.

    Substrate carrier system and method for using the same
    4.
    发明授权
    Substrate carrier system and method for using the same 有权

    公开(公告)号：US10153191B2

    公开(公告)日：2018-12-11

    申请号：US15122736

    申请日：2015-03-20

    Applicant: Applied Materials, Inc.

    Inventor： Zuoqian Wang ,  John M. White

    IPC: H01L21/683 ,  H01L51/56 ,  H01L51/00

    Abstract: A substrate carrier system is provided. The substrate carrier system includes a substrate carrier body, an electrode assembly, a support base, and a controller. The substrate carrier body has a substrate supporting surface, and an electrode assembly is disposed in the substrate carrier body. The electrode assembly includes a plurality of laterally spaced apart electrode sets. Each electrode set includes a first electrode interleaved with a second electrode. The support base supports the substrate carrier body. The controller is configured to: select a first group of the electrode sets and a second group of the electrode sets from the plurality of the electrode sets; operate the first group of the electrode sets in a first chucking mode; simultaneously operate the second group of the electrode sets in a second chucking mode; and selectively switch at least one electrode set from the first group to the second group.

    Multilayer passivation or etch stop TFT
    7.
    发明授权
    Multilayer passivation or etch stop TFT 有权
    多层钝化或蚀刻停止TFT

    公开(公告)号：US09590113B2

    公开(公告)日：2017-03-07

    申请号：US14773209

    申请日：2014-03-04

    Applicant: Applied Materials, Inc.

    Inventor： Dong-kil Yim ,  Tae Kyung Won ,  Seon-Mee Cho ,  John M. White

    IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L29/24

    CPC classification number: H01L29/66969 ,  H01L21/467 ,  H01L29/24 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/7869

    Abstract: The present invention generally relates to TFTs and methods for fabricating TFTs. For either back channel etch TFTs or for etch stop TFTs, multiple layers for the passivation layer or the etch stop layers permits a very dense capping layer to be formed over a less dense back channel protection layer. The capping layer can be sufficiently dense so that few pin holes are present and thus, hydrogen may not pass through to the semiconductor layer. As such, hydrogen containing precursors may be used for the capping layer deposition.

    Abstract translation: 本发明一般涉及TFT和TFT的制造方法。 对于背沟道蚀刻TFT或蚀刻停止TFT，用于钝化层或蚀刻停止层的多个层允许在较不致密的背沟道保护层上形成非常密集的覆盖层。 封盖层可以是足够密实的，从而存在很少的针孔，因此氢不能通过半导体层。 因此，含氢前体可以用于覆盖层沉积。

    Buffer layers for metal oxide semiconductors for TFT
    8.
    发明授权
    Buffer layers for metal oxide semiconductors for TFT 有权
    用于TFT的金属氧化物半导体的缓冲层

    公开(公告)号：US09385239B2

    公开(公告)日：2016-07-05

    申请号：US14203433

    申请日：2014-03-10

    Applicant: Applied Materials, Inc.

    Inventor： Kurtis Leschkies ,  Steven Verhaverbeke ,  Robert Visser ,  John M. White ,  Yan Ye ,  Dong-Kil Yim

    IPC: H01L29/786 ,  H01L29/49

    CPC classification number: H01L29/7869 ,  H01L29/4908

    Abstract: The present invention generally relates to a thin film semiconductor device having a buffer layer formed between the semiconductor layer and one or more layers. In one embodiment, a thin film semiconductor device includes a semiconductor layer having a first work function and a first electron affinity level, a buffer layer having a second work function greater than the first work function and a second electron affinity level that is less than the first electron affinity level; and a gate dielectric layer having a third work function less than the second work function and a third electron affinity level that is greater than the second electron affinity level.

    Abstract translation: 本发明一般涉及一种在半导体层与一层或多层之间形成缓冲层的薄膜半导体器件。 在一个实施例中，薄膜半导体器件包括具有第一功函数和第一电子亲和度的半导体层，具有大于第一功函数的第二功函数的缓冲层和小于第一功函数的第二电子亲和度 第一电子亲和力水平; 以及具有小于第二功函数的第三功函数和大于第二电子亲和度的第三电子亲和度的栅介质层。

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