公开(公告)号：US20240110284A1

公开(公告)日：2024-04-04

申请号：US18372792

申请日：2023-09-26

Applicant: Applied Materials, Inc.

Inventor： Lulu XIONG ,  Kevin Hsiao ,  Chris LIU ,  Chieh-Wen LO ,  Sean M. SEUTTER ,  Deenesh PADHI ,  Prayudi LIANTO ,  Peng SUO ,  Guan Huei SEE ,  Zongbin WANG ,  Shengwei ZENG ,  Balamurugan RAMASAMY

IPC: C23C16/505 ,  C23C16/04 ,  C23C16/32 ,  C23C16/56 ,  H01J37/32

CPC classification number: C23C16/505 ,  C23C16/045 ,  C23C16/325 ,  C23C16/56 ,  H01J37/32165 ,  H01J37/3244 ,  H01J2237/3321

Abstract: A method of processing a substrate is disclosed which includes depositing a layer in a processing chamber on a field region, a sidewall region, and a fill region of a feature of the substrate, wherein a hardness of a portion of the layer deposited on the sidewall region is lower than a hardness of a portion of the layer deposited on the field region, and lower than a hardness of a portion of the layer deposited on the fill region.

公开(公告)号：US20210249270A1

公开(公告)日：2021-08-12

申请号：US17242375

申请日：2021-04-28

Applicant: Applied Materials, Inc.

Inventor： Gaurav THAREJA ,  Keyvan KASHEFIZADEH ,  Xikun WANG ,  Anchuan WANG ,  Sanjay NATARAJAN ,  Sean M. SEUTTER ,  Dong WU

IPC: H01L21/28 ,  H01L29/45 ,  H01L29/49 ,  H01L21/283

Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.

公开(公告)号：US20200258744A1

公开(公告)日：2020-08-13

申请号：US16442797

申请日：2019-06-17

Applicant: Applied Materials, Inc.

Inventor： Gaurav THAREJA ,  Keyvan KASHEFIZADEH ,  Xikun WANG ,  Anchuan WANG ,  Sanjay NATARAJAN ,  Sean M. SEUTTER ,  Dong Wu

IPC: H01L21/28 ,  H01L21/283 ,  H01L29/49 ,  H01L29/45

Abstract: A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.