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公开(公告)号:US20150371907A1
公开(公告)日:2015-12-24
申请号:US14312470
申请日:2014-06-23
发明人: Wei Lu , Zhihong Wang , Wen-Chiang Tu , Zhefu Wang , Hassan G. Iravani , Boguslaw A. Swedek , Fred C. Redeker , William H. McClintock
IPC分类号: H01L21/66 , H01L21/306
CPC分类号: H01L22/14 , H01L21/3212 , H01L22/26 , H01L22/30
摘要: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.
摘要翻译: 用于制造集成电路的衬底具有具有多个导电互连的层。 衬底包括半导体本体,设置在半导体本体上的电介质层,设置在电介质层中的第一沟槽中的导电材料的多条导电线,以提供导电互连,以及设置导电材料的闭合导电环结构 在介质层的第二沟槽中。 闭合的导电回路不与任何导电线电连接。
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公开(公告)号:US20190035699A1
公开(公告)日:2019-01-31
申请号:US16150009
申请日:2018-10-02
发明人: Wei Lu , Zhefu Wang , Zhihong Wang , Hassan G. Iravani , Dominic J. Benvegnu , Ingemar Carlsson , Boguslaw A. Swedek , Wen-Chiang Tu
IPC分类号: H01L21/66 , H01L21/321 , B24B37/04 , B24B37/013
摘要: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.
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公开(公告)号:US20170365532A1
公开(公告)日:2017-12-21
申请号:US15694632
申请日:2017-09-01
发明人: Wei Lu , Zhefu Wang , Zhihong Wang , Hassan G. Iravani , Dominic J. Benvegnu , Ingemar Carlsson , Boguslaw A. Swedek , Wen-Chiang Tu
IPC分类号: H01L21/66 , B24B37/04 , H01L21/321 , B24B37/013
CPC分类号: H01L22/26 , B24B37/013 , B24B37/04 , H01L21/3212 , H01L22/14
摘要: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.
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公开(公告)号:US09754846B2
公开(公告)日:2017-09-05
申请号:US14312503
申请日:2014-06-23
发明人: Wei Lu , Zhefu Wang , Zhihong Wang , Hassan G. Iravani , Dominic J. Benvegnu , Ingemar Carlsson , Boguslaw A. Swedek , Wen-Chiang Tu
IPC分类号: G06F19/00 , H01L21/8242 , H01L21/66 , B24B37/04 , B24B37/013 , H01L21/321
CPC分类号: H01L22/26 , B24B37/013 , B24B37/04 , H01L21/3212 , H01L22/14
摘要: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.
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公开(公告)号:US10199281B2
公开(公告)日:2019-02-05
申请号:US15891290
申请日:2018-02-07
发明人: Wei Lu , Zhihong Wang , Wen-Chiang Tu , Zhefu Wang , Hassan G. Iravani , Boguslaw A. Swedek , Fred C. Redeker , William H. McClintock
IPC分类号: H01L21/66 , H01L21/321
摘要: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.
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公开(公告)号:US20180166347A1
公开(公告)日:2018-06-14
申请号:US15891290
申请日:2018-02-07
发明人: Wei Lu , Zhihong Wang , Wen-Chiang Tu , Zhefu Wang , Hassan G. Iravani , Boguslaw A. Swedek , Fred C. Redeker , William H. McClintock
IPC分类号: H01L21/66 , H01L21/321
CPC分类号: H01L22/14 , H01L21/3212 , H01L22/26 , H01L22/30
摘要: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.
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公开(公告)号:US10741459B2
公开(公告)日:2020-08-11
申请号:US16150009
申请日:2018-10-02
发明人: Wei Lu , Zhefu Wang , Zhihong Wang , Hassan G. Iravani , Dominic J. Benvegnu , Ingemar Carlsson , Boguslaw A. Swedek , Wen-Chiang Tu
IPC分类号: B24B37/013 , B24B37/04 , H01L21/66 , H01L21/321 , H01L21/32
摘要: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.
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公开(公告)号:US10103073B2
公开(公告)日:2018-10-16
申请号:US15694632
申请日:2017-09-01
发明人: Wei Lu , Zhefu Wang , Zhihong Wang , Hassan G. Iravani , Dominic J. Benvegnu , Ingemar Carlsson , Boguslaw A. Swedek , Wen-Chiang Tu
IPC分类号: H01L21/00 , H01L21/302 , H01L21/66 , H01L21/321 , B24B37/013 , B24B37/04
摘要: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.
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公开(公告)号:US09911664B2
公开(公告)日:2018-03-06
申请号:US14312470
申请日:2014-06-23
发明人: Wei Lu , Zhihong Wang , Wen-Chiang Tu , Zhefu Wang , Hassan G. Iravani , Boguslaw A. Swedek , Fred C. Redeker , William H. McClintock
IPC分类号: H01L23/58 , H01L21/66 , H01L21/321
CPC分类号: H01L22/14 , H01L21/3212 , H01L22/26 , H01L22/30
摘要: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.
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公开(公告)号:US20150371913A1
公开(公告)日:2015-12-24
申请号:US14312503
申请日:2014-06-23
发明人: Wei Lu , Zhefu Wang , Zhihong Wang , Hassan G. Iravani , Dominic J. Benvegnu , Ingemar Carlsson , Boguslaw A. Swedek , Wen-Chiang Tu
IPC分类号: H01L21/66 , B24B37/013 , B24B37/04 , H01L21/306 , H01L21/67
CPC分类号: H01L22/26 , B24B37/013 , B24B37/04 , H01L21/3212 , H01L22/14
摘要: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.
摘要翻译: 在具有具有多个导电互连层的集成电路的制造中,抛光衬底层以提供集成电路的层。 衬底的层包括提供导电互连的导线。 衬底层包括在沟槽中由导电材料形成的闭合导电环路。 使用感应监测系统监测沟槽中导电材料的深度,并产生信号。 监测包括产生间歇地通过闭合导电回路的磁场。 从信号中提取随时间变化的值序列,表示导电材料随着时间的深度的值序列。
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