公开(公告)号：US20190237111A1

公开(公告)日：2019-08-01

申请号：US15881704

申请日：2018-01-26

Applicant: Arm Limited

Inventor： Vivek Nautiyal ,  Satinderjit Singh ,  Abhishek B. Akkur ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Jungtae Kwon ,  Jitendra Dasani ,  Manoj Puthan Purayil

IPC: G11C5/06 ,  G11C7/06

CPC classification number: G11C5/063 ,  G11C7/06

Abstract: Various implementations described herein are directed to an integrated circuit having multiple banks of memory cells and a local input/output (IO) component for each bank of the multiple banks. The integrated circuit may include multiple signal lines that are coupled to the multiple banks with the local IO components. At least one signal line of the multiple signal lines is wider than one or more of the other signal lines.

公开(公告)号：US09767870B1

公开(公告)日：2017-09-19

申请号：US15238551

申请日：2016-08-16

Applicant: ARM Limited

Inventor： Rajiv Kumar Roy ,  Kanika Malik ,  Manoj Puthan Purayil ,  Vikash

IPC: G11C5/14 ,  G11C7/10 ,  G11C7/06 ,  G11C8/10

CPC classification number: G11C5/14 ,  G11C7/065 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/417 ,  G11C11/418

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include core circuitry having an array of memory cells and a row decoder that accesses each of the memory cells via a selected wordline and a wordline signal. The core circuitry may operate at a first supply voltage. The integrated circuit may include periphery circuitry having a column decoder that accesses each of the memory cells via a selected bitline. The periphery circuitry may operate at a second supply voltage that is different than the first supply voltage. The periphery circuitry may include voltage differential sensing circuitry that may compare the first supply voltage to the second supply voltage, sense a voltage differential between the first and second supply voltages, and delay the wordline signal when the voltage differential is greater than a threshold voltage.