公开(公告)号：US09911510B1

公开(公告)日：2018-03-06

申请号：US15288832

申请日：2016-10-07

Applicant: ARM Limited

Inventor： Jungtae Kwon ,  Young Suk Kim ,  Vivek Nautiyal ,  Pranay Prabhat ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi ,  Satinderjit Singh ,  Lalit Gupta

IPC: G11C29/00 ,  G11C11/418 ,  G11C11/412

CPC classification number: G11C29/76 ,  G11C8/04 ,  G11C11/413 ,  G11C11/418

Abstract: Various implementations described herein are directed to an integrated circuit having a memory cell array with multiple rows of memory cells including at least one redundant row of memory cells. The memory cell array may be partitioned into multiple regions of memory cells including a first region of memory cells corresponding to a first part of the redundant row of memory cells and a second region of memory cells corresponding to a second part of the redundant row of memory cells. The integrated circuit may include wordline driver circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells. In some instances, the integrated circuit may include row shift circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells.

公开(公告)号：US08971133B1

公开(公告)日：2015-03-03

申请号：US14037413

申请日：2013-09-26

Applicant: ARM Limited

Inventor： Bo Zheng ,  Jungtae Kwon ,  Gus Yeung ,  Yew Keong Chong

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/12 ,  G06F17/50

CPC classification number: G11C7/12 ,  G11C7/1096

Abstract: A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells.

Abstract translation: 具有连接到核心电压电平的存储器单元阵列的存储器件，以及用于执行写入操作以便将数据写入到多个寻址的存储器单元中的存取电路。 在执行写入操作之前，至少与包含寻址的存储器单元的阵列中的每列相关联的位线被预充电到外围电压电平。 然后，字线驱动器电路被配置为在与包含寻址的存储器单元的阵列的行相关联的字线上的核心电压电平处断言字线信号。 写复用驱动器电路断言多路复用控制信号以写入多路复用电路，然后根据多路复用器控制信号将每个寻址的存储器单元的位线耦合到写入驱动器电路，该多路复用器控制信号标识哪个列包含寻址的存储器单元。

公开(公告)号：US20190237111A1

公开(公告)日：2019-08-01

申请号：US15881704

申请日：2018-01-26

Applicant: Arm Limited

Inventor： Vivek Nautiyal ,  Satinderjit Singh ,  Abhishek B. Akkur ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Jungtae Kwon ,  Jitendra Dasani ,  Manoj Puthan Purayil

IPC: G11C5/06 ,  G11C7/06

CPC classification number: G11C5/063 ,  G11C7/06

Abstract: Various implementations described herein are directed to an integrated circuit having multiple banks of memory cells and a local input/output (IO) component for each bank of the multiple banks. The integrated circuit may include multiple signal lines that are coupled to the multiple banks with the local IO components. At least one signal line of the multiple signal lines is wider than one or more of the other signal lines.

公开(公告)号：US09990972B1

公开(公告)日：2018-06-05

申请号：US15357691

申请日：2016-11-21

Applicant: ARM Limited

Inventor： Jungtae Kwon ,  Young Suk Kim

IPC: G11C8/00 ,  G11C7/22 ,  G11C7/12 ,  G11C7/14

CPC classification number: G11C7/22 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/14 ,  G11C7/227 ,  G11C8/14

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a memory bank having an array of memory cells that are accessible via a selected wordline and a pair of complementary bitlines. The integrated circuit may include a dummy wordline coupled to each of the pair of complementary bitlines via a pair of coupling capacitors. The dummy wordline may mimic the selected wordline. During transitions of the pair of complementary bitlines between first and second logic states, the dummy wordline may receive coupling capacitance from the pair of complementary bitlines via the pair of coupling capacitors.

公开(公告)号：US20200185014A1

公开(公告)日：2020-06-11

申请号：US16213832

申请日：2018-12-07

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Jungtae Kwon ,  Nicolaas Klarinus Johannes VAN WINKELHOFF

IPC: G11C8/10

Abstract: Various implementations described herein refer to an integrated circuit having a memory cell array with a first number of rows and a second number of rows. The integrated circuit may include a first pre-decoder that receives a row address and selects a first row from the first number of rows based on the row address. The integrated circuit may include a second pre-decoder that receives the row address from the first pre-decoder and selects a second row from the second number of rows based on the row address received from the first pre-decoder. The integrated circuit may include a single row decoder that receives the row address and selects either the first row or the second row based on a row selection bit from the row address.

公开(公告)号：US20180144780A1

公开(公告)日：2018-05-24

申请号：US15357691

申请日：2016-11-21

Applicant: ARM Limited

Inventor： Jungtae Kwon ,  Young Suk Kim

IPC: G11C7/22 ,  G11C7/12 ,  G11C7/14

CPC classification number: G11C7/22 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/14 ,  G11C7/227 ,  G11C8/14

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a memory bank having an array of memory cells that are accessible via a selected wordline and a pair of complementary bitlines. The integrated circuit may include a dummy wordline coupled to each of the pair of complementary bitlines via a pair of coupling capacitors. The dummy wordline may mimic the selected wordline. During transitions of the pair of complementary bitlines between first and second logic states, the dummy wordline may receive coupling capacitance from the pair of complementary bitlines via the pair of coupling capacitors.