公开(公告)号：US10452803B2

公开(公告)日：2019-10-22

申请号：US15418593

申请日：2017-01-27

Applicant: ARM Limited

Inventor： Karen Lee Delk

IPC: G06F9/455 ,  G06F17/50

Abstract: Various implementations described herein are directed to an apparatus. The apparatus may include a region identifier module that receives user defined parameters for modifying a power grid layout and identifies a region of the power grid layout for strap insertion based on the user defined parameters. The apparatus may include a track identifier module that identifies track locations in the region of the power grid layout for strap insertion. The apparatus may include a strap placement module that inserts at least one strap in the region of the power grid layout based on pre-determined rules for strap insertion.

公开(公告)号：US09690889B2

公开(公告)日：2017-06-27

申请号：US15239991

申请日：2016-08-18

Applicant: ARM LIMITED

Inventor： Marlin Wayne Frederick, Jr. ,  Karen Lee Delk ,  Lena Ahlen ,  James Dennis Dodrill

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5081 ,  G06F2217/84

Abstract: A static timing analysis method that determines an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.

公开(公告)号：US11380618B2

公开(公告)日：2022-07-05

申请号：US15887972

申请日：2018-02-02

Applicant: Arm Limited

Inventor： Marlin Wayne Frederick, Jr. ,  Karen Lee Delk

IPC: H01L23/528 ,  H02J1/08 ,  H01L23/522 ,  H01L23/535 ,  H01L23/538 ,  H01L23/64 ,  H01L27/02

Abstract: Various implementations described herein are directed to an integrated circuit having a power gate cell and a first power distribution grid. The integrated circuit may include a second power distribution grid aligned with and disposed above the power gate cell. The second power distribution grid may be disposed between the power gate cell and the first power distribution grid.

公开(公告)号：US10417371B2

公开(公告)日：2019-09-17

申请号：US15418602

申请日：2017-01-27

Applicant: ARM Limited

Inventor： Karen Lee Delk ,  Marlin Wayne Frederick, Jr. ,  Ravindra Narayana Rao

IPC: G06F17/50

Abstract: Various implementations described herein are directed to an apparatus. The apparatus may include a region identifier module that receives a floorplan of an integrated circuit, identifies a standard cell region between already placed functional blocks of the floorplan, and sub-divides the standard cell region into multiple sub-regions. The apparatus may include a region analyzer module that analyzes each sub-region of the multiple sub-regions to determine a number of already placed power straps that exist within a boundary of each sub-region. The apparatus may include a strap placement module that inserts one or more additional power straps in each sub-region based on user defined parameters for each sub-region, if it is determined that the number of already placed power straps is inconsistent with the user defined parameters for each sub-region.

公开(公告)号：US20190244900A1

公开(公告)日：2019-08-08

申请号：US15887972

申请日：2018-02-02

Applicant: Arm Limited.

Inventor： Marlin Wayne Frederick, JR. ,  Karen Lee Delk

IPC: H01L23/528 ,  H01L27/02 ,  H01L23/64

CPC classification number: H01L23/5286 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H01L23/5381 ,  H01L23/5386 ,  H01L23/647 ,  H01L27/0207 ,  H02J1/08

Abstract: Various implementations described herein are directed to an integrated circuit having a power gate cell and a first power distribution grid. The integrated circuit may include a second power distribution grid aligned with and disposed above the power gate cell. The second power distribution grid may be disposed between the power gate cell and the first power distribution grid.

公开(公告)号：US11152139B2

公开(公告)日：2021-10-19

申请号：US16036673

申请日：2018-07-16

Applicant: Arm Limited

Inventor： Marlin Wayne Frederick, Jr. ,  Karen Lee Delk ,  Sharrone Rena Smith

IPC: H01B13/00 ,  H02B3/00 ,  G06F30/392 ,  H01L27/02 ,  G06F119/06 ,  H01L27/118

Abstract: Various implementations described herein refer to a method. The method may include providing multiple rows of cells having porosity segments including a first row of cells having first porosity segments and a second row of cells having second porosity segments that are arranged differently than the first porosity segments. The method may include providing multiple power distribution rails for the multiple rows of cells having a first power distribution rail and a second power distribution rail disposed adjacent to the first row of cells and the second row of cells. The method may include adjusting position of the second row of cells with respect to the first row of cells to align one or more of the second porosity segments with one or more of the first porosity segments to enable rail stitch insertion between the first power distribution rail and the second power distribution rail.

公开(公告)号：US20180218108A1

公开(公告)日：2018-08-02

申请号：US15418613

申请日：2017-01-27

Applicant: ARM Limited

Inventor： Ravindra Narayana Rao ,  Marlin Wayne Frederick, JR. ,  Karen Lee Delk ,  Stefan Charles Creaser

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/78

Abstract: Various implementations described herein are directed to an apparatus having a receiver module that receives a floorplan of an integrated circuit having power gates, an obstruction, and a control pin for providing a sleep signal. The apparatus may include an identifier module that identifies where the obstruction interrupts a sequence of the power gates, organizes the sequence of the power gates into a column, and divides the column into segments in which a first segment lies below the obstruction, a second segment lies above the obstruction, and a third segment is offset from the first and second segments. The apparatus may include a stitcher module that performs sleep signal stitching for the integrated circuit by distributing a sleep signal from the control pin to the power gates that includes each power gate in each of the first, second, and third segments.

公开(公告)号：US20180218106A1

公开(公告)日：2018-08-02

申请号：US15418593

申请日：2017-01-27

Applicant: ARM Limited

Inventor： Karen Lee Delk

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F2217/06 ,  G06F2217/12

Abstract: Various implementations described herein are directed to an apparatus. The apparatus may include a region identifier module that receives user defined parameters for modifying a power grid layout and identifies a region of the power grid layout for strap insertion based on the user defined parameters. The apparatus may include a track identifier module that identifies track locations in the region of the power grid layout for strap insertion. The apparatus may include a strap placement module that inserts at least one strap in the region of the power grid layout based on pre-determined rules for strap insertion.

公开(公告)号：US20200020464A1

公开(公告)日：2020-01-16

申请号：US16036673

申请日：2018-07-16

Applicant: Arm Limited

Inventor： Marlin Wayne Frederick, JR. ,  Karen Lee Delk ,  Sharrone Rena Smith

IPC: H01B13/00

Abstract: Various implementations described herein refer to a method. The method may include providing multiple rows of cells having porosity segments including a first row of cells having first porosity segments and a second row of cells having second porosity segments that are arranged differently than the first porosity segments. The method may include providing multiple power distribution rails for the multiple rows of cells having a first power distribution rail and a second power distribution rail disposed adjacent to the first row of cells and the second row of cells. The method may include adjusting position of the second row of cells with respect to the first row of cells to align one or more of the second porosity segments with one or more of the first porosity segments to enable rail stitch insertion between the first power distribution rail and the second power distribution rail.

公开(公告)号：US10210303B2

公开(公告)日：2019-02-19

申请号：US15418613

申请日：2017-01-27

Applicant: ARM Limited

Inventor： Ravindra Narayana Rao ,  Marlin Wayne Frederick, Jr. ,  Karen Lee Delk ,  Stefan Charles Creaser

IPC: G06F17/50

Abstract: Various implementations described herein are directed to an apparatus having a receiver module that receives a floorplan of an integrated circuit having power gates, an obstruction, and a control pin for providing a sleep signal. The apparatus can include an identifier module that identifies where the obstruction interrupts a sequence of the power gates, organizes the sequence of the power gates into a column, and divides the column into segments in which a first segment lies below the obstruction, a second segment lies above the obstruction, and a third segment is offset from the first segment and the second segment. The apparatus can include a stitcher module that performs a sleep signal stitching for the integrated circuit by distributing the sleep signal from the control pin to the power gates that include each power gate in each of the first segment, the second segment, and the third segment.