公开(公告)号：US20190244900A1

公开(公告)日：2019-08-08

申请号：US15887972

申请日：2018-02-02

Applicant: Arm Limited.

Inventor： Marlin Wayne Frederick, JR. ,  Karen Lee Delk

IPC: H01L23/528 ,  H01L27/02 ,  H01L23/64

CPC classification number: H01L23/5286 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H01L23/5381 ,  H01L23/5386 ,  H01L23/647 ,  H01L27/0207 ,  H02J1/08

Abstract: Various implementations described herein are directed to an integrated circuit having a power gate cell and a first power distribution grid. The integrated circuit may include a second power distribution grid aligned with and disposed above the power gate cell. The second power distribution grid may be disposed between the power gate cell and the first power distribution grid.

公开(公告)号：US20190026417A1

公开(公告)日：2019-01-24

申请号：US16140461

申请日：2018-09-24

Applicant: Arm Limited

Inventor： Paul de Dood ,  Marlin Wayne Frederick, JR. ,  Jerry Chaoyuan Wang ,  Brian Tracy Cline ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Sriram Thyagarajan ,  Gus Yeung ,  Daniel J. Albers ,  David William Granda

IPC: G06F17/50

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

公开(公告)号：US20170186745A1

公开(公告)日：2017-06-29

申请号：US14981449

申请日：2015-12-28

Applicant: ARM Limited

Inventor： Jean-Luc Pelloie ,  Marlin Wayne Frederick, JR.

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/092 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207

Abstract: Various implementations described herein are directed to an integrated circuit with mitigated resistance. The integrated circuit may include a cell having a plurality of transistors including a first transistor of a first type and a second transistor of a second type that is different from the first type. The integrated circuit may include a first wire coupling the first transistor to the second transistor. The integrated circuit may include a second wire coupling the first wire to an output routing wire. The integrated circuit may include a redundant wire further coupling the first wire to the output routing wire.

公开(公告)号：US20220188496A1

公开(公告)日：2022-06-16

申请号：US17685166

申请日：2022-03-02

Applicant: Arm Limited

Inventor： Sharath Koodali Edathil ,  Marlin Wayne Frederick, JR.

IPC: G06F30/373 ,  G06F30/398 ,  G06F30/394 ,  G06F30/327

Abstract: Various implementations described herein refer to a method. The method may be configured to synthesize standard cells for a physical design having a power supply net with power supply rails. The method may be configured to employ a place-and-route tool so as to define edge-types for each standard cell of the standard cells in the physical design based on the power supply net and the power supply rails that touch at least one edge of each standard cell of the standard cells.

公开(公告)号：US20200020464A1

公开(公告)日：2020-01-16

申请号：US16036673

申请日：2018-07-16

Applicant: Arm Limited

Inventor： Marlin Wayne Frederick, JR. ,  Karen Lee Delk ,  Sharrone Rena Smith

IPC: H01B13/00

Abstract: Various implementations described herein refer to a method. The method may include providing multiple rows of cells having porosity segments including a first row of cells having first porosity segments and a second row of cells having second porosity segments that are arranged differently than the first porosity segments. The method may include providing multiple power distribution rails for the multiple rows of cells having a first power distribution rail and a second power distribution rail disposed adjacent to the first row of cells and the second row of cells. The method may include adjusting position of the second row of cells with respect to the first row of cells to align one or more of the second porosity segments with one or more of the first porosity segments to enable rail stitch insertion between the first power distribution rail and the second power distribution rail.

公开(公告)号：US20180218107A1

公开(公告)日：2018-08-02

申请号：US15418602

申请日：2017-01-27

Applicant: ARM Limited

Inventor： Karen Lee Delk ,  Marlin Wayne Frederick, JR. ,  Ravindra Narayana Rao

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5081 ,  G06F2217/78

Abstract: Various implementations described herein are directed to an apparatus. The apparatus may include a region identifier module that receives a floorplan of an integrated circuit, identifies a standard cell region between already placed functional blocks of the floorplan, and sub-divides the standard cell region into multiple sub-regions. The apparatus may include a region analyzer module that analyzes each sub-region of the multiple sub-regions to determine a number of already placed power straps that exist within a boundary of each sub-region. The apparatus may include a strap placement module that inserts one or more additional power straps in each sub-region based on user defined parameters for each sub-region, if it is determined that the number of already placed power straps is inconsistent with the user defined parameters for each sub-region.

公开(公告)号：US20210167013A1

公开(公告)日：2021-06-03

申请号：US17175640

申请日：2021-02-13

Applicant: Arm Limited

Inventor： Marlin Wayne Frederick, JR. ,  Karen Lee Delk

IPC: H01L23/528 ,  H01L23/50 ,  H01L21/66 ,  H01L21/768 ,  G06F30/398 ,  H01L25/00 ,  G06F30/394 ,  G06F119/06 ,  H01L21/60

Abstract: An apparatus, a method, and a method of manufacturing an integrated circuit having a metal layer, metal wires within the metal layer being configured such that they have a regular pattern.

公开(公告)号：US20210019463A1

公开(公告)日：2021-01-21

申请号：US17062567

申请日：2020-10-03

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Gus Yeung ,  Marlin Wayne Frederick, JR. ,  Sriram Thyagarajan

IPC: G06F30/39 ,  G06F30/30 ,  G06F30/398

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

公开(公告)号：US20180225402A9

公开(公告)日：2018-08-09

申请号：US14528314

申请日：2014-10-30

Applicant: ARM Limited

Inventor： Paul DE DOOD ,  Marlin Wayne Frederick, JR. ,  Jerry Chaoyuan Wang ,  Brian Douglas Ngai Lee ,  Brian Tracy Cline ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Sriram Thyagarajan ,  Gus Yeung ,  Yanbin Jiang ,  Emmanuel Jean Marie Olivier Pacaud ,  Matthieu Domonique Henri Pauly ,  Sylvia Xiuhui Li ,  Thanusree Achuthan ,  Daniel J. Albers ,  David William Granda

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

公开(公告)号：US20180211914A1

公开(公告)日：2018-07-26

申请号：US15873874

申请日：2018-01-17

Applicant: ARM Limited

Inventor： Marlin Wayne Frederick, JR. ,  Karen Lee Delk

IPC: H01L23/528 ,  H01L23/50 ,  H01L25/00 ,  H01L21/66

Abstract: An apparatus, a method, and a method of manufacturing an integrated circuit having a metal layer, metal wires within the metal layer being configured such that they have a regular pattern.