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    Profile engineered, electrically active thin film devices
    1.
    发明授权
    Profile engineered, electrically active thin film devices 有权
    型材设计，电活性薄膜器件

    公开(公告)号：US08426905B2

    公开(公告)日：2013-04-23

    申请号：US12243880

    申请日：2008-10-01

    申请人： Arvind Kamath ,  Erik Scher ,  Patrick Smith ,  Aditi Chandra ,  Steven Molesa

    发明人： Arvind Kamath ,  Erik Scher ,  Patrick Smith ,  Aditi Chandra ,  Steven Molesa

    IPC分类号： H01L29/788

    CPC分类号： H01L21/36 ,  C23C18/08 ,  C23C18/122 ,  C23C18/1245 ,  C23C18/1295 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/28273 ,  H01L21/28518 ,  H01L21/288 ,  H01L21/76871 ,  H01L21/76895 ,  H01L27/1285 ,  H01L27/1292 ,  H01L28/40 ,  H01L29/0657 ,  H01L29/66143 ,  H01L29/6675 ,  H01L29/7881 ,  H01L29/872 ,  H05K1/16 ,  H05K1/162 ,  H05K3/125 ,  H05K2201/098

    摘要： The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch.

    摘要翻译： 本发明涉及具有平滑和/或圆顶形轮廓的电介质，导体和/或半导体层的电活性器件（例如，电容器，晶体管，二极管，浮动栅极存储单元等）和形成这种器件的方法 通过沉积或印刷（例如喷墨印刷）包括半导体，金属或电介质前体的油墨组合物。 平滑和/或圆顶形的横截面轮廓允许平滑的拓扑转变而没有尖锐的步骤，防止沉积期间的特征不连续性，并允许随后沉积的结构的更完整的阶梯覆盖。 本发明的轮廓允许通过热氧化均匀生长氧化物层，以及基本均匀的结构蚀刻速率。 这样的氧化物层可以具有均匀的厚度并且提供基本的电活性特征的基本上完整的覆盖。 均匀蚀刻允许通过简单的各向同性蚀刻来降低电活性结构的临界尺寸的有效方法。

    Profile engineered thin film devices and structures
    2.
    发明授权
    Profile engineered thin film devices and structures 有权
    型材设计薄膜器件和结构

    公开(公告)号：US08822301B2

    公开(公告)日：2014-09-02

    申请号：US13791721

    申请日：2013-03-08

    申请人： Arvind Kamath ,  Erik Scher ,  Patrick Smith ,  Aditi Chandra ,  Steven Molesa

    发明人： Arvind Kamath ,  Erik Scher ,  Patrick Smith ,  Aditi Chandra ,  Steven Molesa

    IPC分类号： H01L21/20

    CPC分类号： H01L21/36 ,  C23C18/08 ,  C23C18/122 ,  C23C18/1245 ,  C23C18/1295 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/28273 ,  H01L21/28518 ,  H01L21/288 ,  H01L21/76871 ,  H01L21/76895 ,  H01L27/1285 ,  H01L27/1292 ,  H01L28/40 ,  H01L29/0657 ,  H01L29/66143 ,  H01L29/6675 ,  H01L29/7881 ,  H01L29/872 ,  H05K1/16 ,  H05K1/162 ,  H05K3/125 ,  H05K2201/098

    摘要： The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch.

    摘要翻译： 本发明涉及具有平滑和/或圆顶形轮廓的电介质，导体和/或半导体层的电活性器件（例如，电容器，晶体管，二极管，浮动栅极存储单元等）和形成这种器件的方法 通过沉积或印刷（例如喷墨印刷）包括半导体，金属或电介质前体的油墨组合物。 平滑和/或圆顶形的横截面轮廓允许平滑的拓扑转变而没有尖锐的步骤，防止沉积期间的特征不连续性，并允许随后沉积的结构的更完整的阶梯覆盖。 本发明的轮廓允许通过热氧化均匀生长氧化物层，以及基本均匀的结构蚀刻速率。 这样的氧化物层可以具有均匀的厚度并且提供基本的电活性特征的基本上完整的覆盖。 均匀蚀刻允许通过简单的各向同性蚀刻来降低电活性结构的临界尺寸的有效方法。

    Print Processing for Patterned Conductor, Semiconductor and Dielectric Materials
    4.
    发明申请
    Print Processing for Patterned Conductor, Semiconductor and Dielectric Materials 有权
    图案导体，半导体和电介质材料的印刷加工

    公开(公告)号：US20090065776A1

    公开(公告)日：2009-03-12

    申请号：US12114741

    申请日：2008-05-02

    申请人： Erik SCHER ,  Steven Molesa ,  Joerg Rockenberger ,  Arvind Kamath ,  Ikuo Mori

    发明人： Erik SCHER ,  Steven Molesa ,  Joerg Rockenberger ,  Arvind Kamath ,  Ikuo Mori

    IPC分类号： H01L29/04 ,  C08L83/00 ,  H01L29/06 ,  H01L29/16 ,  H01L21/208

    CPC分类号： C09D5/24 ,  C09D11/101 ,  C09D11/322 ,  C09D11/36 ,  C09D11/54 ,  H01B3/02 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/28008 ,  H01L27/1292 ,  H01L29/6675 ,  H01L29/78696 ,  Y10T428/24802

    摘要： Embodiments relate to printing features from an ink containing a material precursor. In some embodiments, the material includes an electrically active material, such as a semiconductor, a metal, or a combination thereof. In another embodiment, the material includes a dielectric. The embodiments provide improved printing process conditions that allow for more precise control of the shape, profile and dimensions of a printed line or other feature. The composition(s) and/or method(s) improve control of pinning by increasing the viscosity and mass loading of components in the ink. An exemplary method thus includes printing an ink comprising a material precursor and a solvent in a pattern on the substrate; precipitating the precursor in the pattern to form a pinning line; substantially evaporating the solvent to form a feature of the material precursor defined by the pinning line; and converting the material precursor to the patterned material.

    摘要翻译： 实施例涉及从含有材​​料前体的油墨印刷特征。 在一些实施例中，材料包括电活性材料，例如半导体，金属或其组合。 在另一个实施例中，该材料包括电介质。 这些实施例提供改进的印刷工艺条件，其允许更精确地控制印刷线或其它特征的形状，轮廓和尺寸。 组合物和/或方法通过增加油墨中组分的粘度和质量负载来改善对钉扎的控制。 因此，示例性方法包括在基板上以图案印刷包含材料前体和溶剂的油墨; 以图案沉淀前体以形成钉扎线; 基本上蒸发溶剂以形成由钉扎线限定的材料前体的特征; 并将材料前体转化成图案化材料。

    Surveillance devices with multiple capacitors
    7.
    发明授权
    Surveillance devices with multiple capacitors 有权
    具有多个电容器的监控设备

    公开(公告)号：US08912890B2

    公开(公告)日：2014-12-16

    申请号：US13632745

    申请日：2012-10-01

    申请人： Patrick Smith ,  Criswell Choi ,  James Montague Cleeves ,  Vivek Subramanian ,  Arvind Kamath ,  Steven Molesa

    发明人： Patrick Smith ,  Criswell Choi ,  James Montague Cleeves ,  Vivek Subramanian ,  Arvind Kamath ,  Steven Molesa

    IPC分类号： H04Q5/22

    CPC分类号： H01G4/40 ,  H01G4/38

    摘要： The disclosure relates to surveillance and/or identification devices having capacitors connected in parallel or in series, and methods of making and using such devices. Devices with capacitors connected in parallel, where one capacitor is fabricated with a relatively thick capacitor dielectric and another is fabricated with a relatively thin capacitor dielectric achieve both a high-precision capacitance and a low breakdown voltage for relatively easy surveillance tag deactivation. Devices with capacitors connected in series result in increased lateral dimensions of a small capacitor. This makes the capacitor easier to fabricate using techniques that may have relatively limited resolution capabilities.

    摘要翻译： 本公开涉及具有并联或串联连接的电容器的监视和/或识别装置以及制造和使用这些装置的方法。 具有并联连接电容器的器件，其中一个电容器用相对较厚的电容器电介质制造，另一个电容器由相对薄的电容器电介质制成，实现了高精度电容和低击穿电压，以便相对容易的监视标签去激活。 具有串联连接的电容器的装置增加了小电容器的横向尺寸。 这使得使用可能具有相对有限的分辨能力的技术来制造电容器更容易。

    Methods and software for printing materials onto a substrate
    8.
    发明授权
    Methods and software for printing materials onto a substrate 有权
    将材料印刷到基材上的方法和软件

    公开(公告)号：US08191018B1

    公开(公告)日：2012-05-29

    申请号：US12175423

    申请日：2008-07-17

    申请人： Steven Molesa ,  Erik Scher ,  Patrick Smith ,  Michael Kocsis

    发明人： Steven Molesa ,  Erik Scher ,  Patrick Smith ,  Michael Kocsis

    IPC分类号： G06F17/50 ,  G06F19/00 ,  G06K9/00

    CPC分类号： G06F17/50 ,  G06F17/5081 ,  H05K3/0005 ,  H05K3/12

    摘要： Methods and software for correcting printable circuit layouts. The methods generally including steps of identifying shapes in an input circuit layout, applying a plurality of correction rules to the shapes, and producing an output printed circuit layout in accordance with the identified shapes and the correction rules. The input circuit layout generally comprises a bitmapped image or other description of at least one printable layer of at least one electronic component, device, or die. Embodiments of the present invention further allow for more precise control of spreading and effective coverage of features (e.g., source/drain terminal regions, gates, capacitors, diodes, interconnects, etc.) on a substrate by a printed ink composition including electronic materials.

    摘要翻译： 可打印电路布局校正的方法和软件。 所述方法通常包括以下步骤：识别输入电路布局中的形状，对形状应用多个校正规则，以及根据所识别的形状和校正规则产生输出印刷电路布局。 输入电路布局通常包括至少一个电子部件，器件或管芯的至少一个可印刷层的位图图像或其它描述。 本发明的实施例还允许通过包括电子材料的印刷油墨组合物更精确地控制基底上的特征（例如，源极/漏极端子区域，栅极，电容器，二极管，互连等）的扩展和有效覆盖。