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    SILICON GERMANIUM FILM FORMATION METHOD AND STRUCTURE
    5.
    发明申请
    SILICON GERMANIUM FILM FORMATION METHOD AND STRUCTURE 审中-公开
    硅锗膜形成方法和结构

    公开(公告)号：US20130009211A1

    公开(公告)日：2013-01-10

    申请号：US13616994

    申请日：2012-09-14

    申请人： Ashima B. Chakravarti ,  Abhishek Dube ,  Dominic J. Schepis

    发明人： Ashima B. Chakravarti ,  Abhishek Dube ,  Dominic J. Schepis

    IPC分类号： H01L29/161 ,  H01L27/092

    CPC分类号： H01L21/823814 ,  H01L21/76224 ,  H01L21/823807

    摘要： Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.

    摘要翻译： 在不使用掩模的情况下实现硅锗在半导体器件中的外延沉积。 使用在沉积硅锗之前与存在的掺杂剂的相互作用引起的成核延迟来确定暴露的衬底表面可以经历外延沉积以在所需部分上形成SiGe层的周期，而在其它部分上基本上没有沉积。 可以改变掺杂剂浓度以在优选的沉积时间内实现期望的厚度。 导致沉积的SiGe基本上没有生长边缘效应。

    Pattern independent Si:C selective epitaxy
    7.
    发明授权
    Pattern independent Si:C selective epitaxy 失效
    图案独立Si：C选择性外延

    公开(公告)号：US07759213B2

    公开(公告)日：2010-07-20

    申请号：US12189344

    申请日：2008-08-11

    申请人： Abhishek Dube ,  Ashima B. Chakravarti ,  Dominic J. Schepis

    发明人： Abhishek Dube ,  Ashima B. Chakravarti ,  Dominic J. Schepis

    IPC分类号： H01L21/76

    CPC分类号： H01L21/02381 ,  H01L21/02529 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/66636 ,  H01L29/7848

    摘要： Trenches are formed in a silicon substrate by etching exposed portions of the silicon substrate. After covering areas on which deposition of Si:C containing material is to be prevented, selective epitaxy is performed in a single wafer chamber at a temperature from about 550° C. to about 600° C. employing a limited carrier gas flow, i.e., at a flow rate less than 12 standard liters per minute to deposit Si:C containing regions at a pattern-independent uniform deposition rate. The inventive selective epitaxy process for Si:C deposition provides a relatively high net deposition rate a high quality Si:C crystal in which the carbon atoms are incorporated into substitutional sites as verified by X-ray diffraction.

    摘要翻译： 通过蚀刻硅衬底的暴露部分在硅衬底中形成沟槽。 在覆盖要防止沉积含Si：C的材料的区域之后，使用有限的载气流在约550℃至约600℃的温度下，在单晶片室中进行选择性外延，即， 以小于12标准升/分钟的流速，以不依赖于图案的均匀沉积速率沉积含Si：C的区域。 用于Si：C沉积的本发明的选择性外延工艺提供了相对较高的净沉积速率，其中通过X射线衍射验证碳原子并入到取代位置的高质量Si：C晶体。

    ELIMINATE NOTCHING IN SI POST SI-RECESS RIE TO IMPROVE EMBEDDED DOPED AND INSTRINSIC SI EPITAZIAL PROCESS
    8.
    发明申请
    ELIMINATE NOTCHING IN SI POST SI-RECESS RIE TO IMPROVE EMBEDDED DOPED AND INSTRINSIC SI EPITAZIAL PROCESS 审中-公开
    消除注意事项，以改善嵌入式印刷和印刷工艺

    公开(公告)号：US20090001430A1

    公开(公告)日：2009-01-01

    申请号：US11771013

    申请日：2007-06-29

    申请人： Ashima B. Chakravarti ,  Renee T. Mo

    发明人： Ashima B. Chakravarti ,  Renee T. Mo

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/823481 ,  H01L21/28176 ,  H01L29/66636 ,  H01L29/7848

    摘要： A dielectric element, and method of manufacturing the same, is disclosed for a semiconductor structure which comprises a substrate having a gate formed on a top surface of the substrate. The substrate and gate define a gap in a region between the gate and the substrate. A specified amount of dielectric on the substrate, at least a portion of which is in the gap, forms the dielectric element which substantially prevents unwanted electrical connectivity between the gate and the substrate.

    摘要翻译： 公开了一种用于半导体结构的电介质元件及其制造方法，该半导体结构包括在衬底的顶表面上形成有栅极的衬底。 衬底和栅极限定栅极和衬底之间的区域中的间隙。 衬底上的至少一部分位于间隙中的指定量的电介质形成基本上防止栅极和衬底之间不必要的电连接的电介质元件。