公开(公告)号：US20210057413A1

公开(公告)日：2021-02-25

申请号：US16954126

申请日：2018-03-28

申请人： Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Intel Corporation

发明人： Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ

IPC分类号： H01L27/092 ,  H01L21/822 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/66 ,  H01L29/06

摘要： An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.

公开(公告)号：US20200098921A1

公开(公告)日：2020-03-26

申请号：US16143222

申请日：2018-09-26

申请人： Willy RACHMADY ,  Patrick MORROW ,  Aaron LILAK ,  Rishabh MEHANDRU ,  Cheng-Ying HUANG ,  Gilbert DEWEY ,  Kimin JUN ,  Ryan KEECH ,  Anh PHAN ,  Ehren MANNEBACH

发明人： Willy RACHMADY ,  Patrick MORROW ,  Aaron LILAK ,  Rishabh MEHANDRU ,  Cheng-Ying HUANG ,  Gilbert DEWEY ,  Kimin JUN ,  Ryan KEECH ,  Anh PHAN ,  Ehren MANNEBACH

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66

摘要： Embodiments include transistor devices and a method of forming the transistor devices. A transistor device includes a first dielectric over a substrate, and vias on a first metal layer, where the first metal layer is on an etch stop layer that is on the first dielectric. The transistor device also includes a second dielectric over the first metal layer, vias, and etch stop layer, where the vias include sidewalls, top surfaces, and bottom surfaces, and stacked transistors on the second dielectric and the top surfaces of the vias, where the sidewalls and top surfaces of the vias are positioned within a footprint of the stacked transistors. The stacked transistors include gate electrodes and first and second transistor layers. The first metal layer includes conductive materials including tungsten or cobalt. The footprint may include a bottom surface of the first transistor layer and a bottom surface of the gate electrodes.

公开(公告)号：US20200006575A1

公开(公告)日：2020-01-02

申请号：US16024682

申请日：2018-06-29

申请人： Gilbert DEWEY ,  Aaron LILAK ,  Van H. LE ,  Abhishek A. SHARMA ,  Tahir GHANI ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Nazila HARATIPOUR ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Shriram SHIVARAMAN

发明人： Gilbert DEWEY ,  Aaron LILAK ,  Van H. LE ,  Abhishek A. SHARMA ,  Tahir GHANI ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Nazila HARATIPOUR ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Shriram SHIVARAMAN

IPC分类号： H01L29/786 ,  H01L29/66

摘要： Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.

公开(公告)号：US20240186398A1

公开(公告)日：2024-06-06

申请号：US18073213

申请日：2022-12-01

申请人： Intel Corporation

发明人： Aaron D. LILAK ,  Anh PHAN ,  Rishabh MEHANDRU ,  Stephen M. CEA ,  Patrick MORROW ,  Jack T. KAVALIEROS ,  Justin WEBER ,  Salim BERRADA

IPC分类号： H01L29/49 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L29/4991 ,  H01L21/28123 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/516 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775

摘要： Integrated circuit structures having cavity spacers, and methods of fabricating integrated circuit structures having cavity spacers, are described. For example, an integrated circuit structure includes a sub-fin structure over a stack of nanowires. A gate structure is vertically around the stack of nanowires. An internal gate spacer is between vertically adjacent ones of the nanowires and adjacent to the gate structure. A trench contact structure is laterally adjacent to a side of the gate structure. A cavity spacer is laterally between the gate structure and the trench contact structure.

公开(公告)号：US20240154011A1

公开(公告)日：2024-05-09

申请号：US18415251

申请日：2024-01-17

申请人： Intel Corporation

发明人： Patrick MORROW ,  Rishabh MEHANDRU ,  Aaron D. LILAK ,  Kimin JUN

IPC分类号： H01L29/417 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L21/823431 ,  H01L27/1266 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/78 ,  H01L29/785 ,  H01L21/2254 ,  H01L29/66545

摘要： An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

公开(公告)号：US20240038857A1

公开(公告)日：2024-02-01

申请号：US18378472

申请日：2023-10-10

申请人： Intel Corporation

发明人： Rishabh MEHANDRU ,  Pratik A. PATEL ,  Ralph T. TROEGER ,  Szuya S. LIAO

IPC分类号： H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/321 ,  H01L29/08 ,  H01L29/40 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/4175 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/32115 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/45 ,  H01L29/4991 ,  H01L29/665 ,  H01L29/6656

摘要： Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.

公开(公告)号：US20240006483A1

公开(公告)日：2024-01-04

申请号：US17855567

申请日：2022-06-30

申请人： Intel Corporation

发明人： Abhishek Anil SHARMA ,  Tahir GHANI ,  Rishabh MEHANDRU ,  Anand S. MURTHY ,  Wilfred GOMES ,  Cory WEBER ,  Sagar SUTHRAM

IPC分类号： H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/0673 ,  H01L29/78618 ,  H01L29/78696 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/7851

摘要： Structures having raised epitaxy on channel structure transistors are described. In an example, an integrated circuit structure includes a channel structure having multi-layer epitaxial source or drain structures thereon, the multi-layer epitaxial source or drain structures having a recess extending there through. A gate dielectric layer is on a bottom and along sides of the recess and laterally surrounded by the epitaxial source or drain structures. A gate electrode is on and laterally surrounded by the gate dielectric layer. The gate electrode has an uppermost surface below an uppermost surface of the gate dielectric layer.

公开(公告)号：US20230352481A1

公开(公告)日：2023-11-02

申请号：US18219374

申请日：2023-07-07

申请人： Intel Corporation

发明人： Aaron D. LILAK ,  Gilbert DEWEY ,  Cheng-Ying HUANG ,  Christopher JEZEWSKI ,  Ehren MANNEBACH ,  Rishabh MEHANDRU ,  Patrick MORROW ,  Anand S. MURTHY ,  Anh PHAN ,  Willy RACHMADY

IPC分类号： H01L27/088 ,  H01L21/768 ,  H01L27/092 ,  H01L23/522 ,  H01L23/00 ,  H01L23/48 ,  H01L21/8258 ,  H01L21/84

CPC分类号： H01L27/0886 ,  H01L21/76898 ,  H01L21/8258 ,  H01L21/845 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/29 ,  H01L24/32 ,  H01L27/0924 ,  H01L24/94 ,  H01L2224/29188 ,  H01L2224/32145

摘要： Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor’s source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor’s channel region and extends downward into a recess that exposes the lower transistor’s source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor’s source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure. Rather, a metal-containing contact structure passes through the epitaxial material of the upper source/drain region and contacts the lower transistor’s source/drain contact structure.

公开(公告)号：US20230131126A1

公开(公告)日：2023-04-27

申请号：US18088469

申请日：2022-12-23

申请人： Intel Corporation

发明人： Szuya S. LIAO ,  Rahul PANDEY ,  Rishabh MEHANDRU ,  Anupama BOWONDER ,  Pratik PATEL

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/08

摘要： Fin shaping, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has substantially vertical upper sidewalls and outwardly tapered lower sidewalls. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20230101725A1

公开(公告)日：2023-03-30

申请号：US17485167

申请日：2021-09-24

申请人： Intel Corporation

发明人： Debaleena NANDI ,  Mauro J. KOBRINSKY ,  Gilbert DEWEY ,  Chi-hing CHOI ,  Harold W. Kennel ,  Brian J. KRIST ,  Ashkar ALIYARUKUNJU ,  Cory BOMBERGER ,  Rushabh SHAH ,  Rishabh MEHANDRU ,  Stephen M. CEA ,  Chanaka MUNASINGHE ,  Anand S. MURTHY ,  Tahir GHANI

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/786

摘要： Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise germanium and boron, and a protective layer comprises silicon, and germanium that at least partially covers the epitaxial source or drain structures. A conductive contact comprising titanium silicide is on the epitaxial source or drain structures.