公开(公告)号：US09952913B2

公开(公告)日：2018-04-24

申请号：US15412198

申请日：2017-01-23

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Sebastien Jouin ,  Stein Danielsen ,  Francois Fosse ,  Thierry Delalande ,  Ivar Holand ,  James Hallman

IPC: G06F13/362 ,  G06F17/30 ,  G06F13/40 ,  G06F13/12 ,  G06F9/52 ,  G06F13/28 ,  G06F13/42

CPC classification number: G06F9/526 ,  G06F11/00 ,  G06F11/004 ,  G06F13/122 ,  G06F13/28 ,  G06F13/362 ,  G06F13/4004 ,  G06F13/4282 ,  G06F17/30362 ,  G06F2201/825

Abstract: Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.

公开(公告)号：US09552385B2

公开(公告)日：2017-01-24

申请号：US13965020

申请日：2013-08-12

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Sebastien Jouin ,  Stein Danielsen ,  Francois Fosse ,  Thierry Delalande ,  Ivar Holand ,  James Hallman

IPC: G06F13/362 ,  G06F17/30 ,  G06F13/40 ,  G06F13/12 ,  G06F11/00

CPC classification number: G06F9/526 ,  G06F11/00 ,  G06F11/004 ,  G06F13/122 ,  G06F13/28 ,  G06F13/362 ,  G06F13/4004 ,  G06F13/4282 ,  G06F17/30362 ,  G06F2201/825

Abstract: Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.

Abstract translation: 公开了针对被配置为保护系统中的一个或多个外围组件的中央外围设备访问控制器（PAC）的实现。 在一些实现中，PAC存储可以由软件设置或清除的数据。 该数据对应于被路由到对应的外围组件的PAC的输出信号。 当数据指示外设“未锁定”时，PAC将允许写入传输到外设组件中的寄存器。 当数据指示外设组件“锁定”时，PAC将拒绝对外设组件中的寄存器进行写入传输，并以错误结束。

公开(公告)号：US09953000B2

公开(公告)日：2018-04-24

申请号：US14826443

申请日：2015-08-14

Applicant: Atmel Corporation

Inventor： Francois Fosse ,  Laurent Le Goffic

IPC: G06F13/00 ,  G06F13/40 ,  G06F13/42 ,  G06F13/364

CPC classification number: G06F13/4068 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4291 ,  G06F2213/0016

Abstract: A device comprising: a bus master, including a bi-directional data and clock lines, configured to produce a select signal output for enabling data transmission on the bi-directional data line to first/second different data busses supporting multiple slave devices configured to receive/transmit data over a respective data bus and to receive a clock signal from the bus master from the clock line; and a de-multiplexer including an input, first and second outputs and a control input, the input coupled to the bi-directional data line of the bus master, first/second outputs of the de-multiplexer coupled to first/second data busses, respectively, and the control input configured to receive the select signal from the bus master that is configured to communicate to a first slave device when the select signal is in a first state, and a second different slave device when the select signal is in a second different state.

公开(公告)号：US20150347344A1

公开(公告)日：2015-12-03

申请号：US14826443

申请日：2015-08-14

Applicant: Atmel Corporation

Inventor： Francois Fosse ,  Laurent Le Goffic

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4291 ,  G06F2213/0016

Abstract: A device comprising: a bus master, including a bi-directional data and clock lines, configured to produce a select signal output for enabling data transmission on the bi-directional data line to first/second different data busses supporting multiple slave devices configured to receive/transmit data over a respective data bus and to receive a clock signal from the bus master from the clock line; and a de-multiplexer including an input, first and second outputs and a control input, the input coupled to the bi-directional data line of the bus master, first/second outputs of the de-multiplexer coupled to first/second data busses, respectively, and the control input configured to receive the select signal from the bus master that is configured to communicate to a first slave device when the select signal is in a first state, and a second different slave device when the select signal is in a second different state.

Abstract translation: 一种设备，包括：总线主机，包括双向数据和时钟线，被配置为产生选择信号输出，用于使所述双向数据线上的数据传输能够支持第一/第二不同数据总线，所述数据总线支持被配置为接收的多个从设备 通过相应的数据总线发送数据，并从时钟线接收总线主机的时钟信号; 以及解复用器，包括输入，第一和第二输出和控制输入，耦合到总线主机的双向数据线的输入，耦合到第一/第二数据总线的解复用器的第一/第二输出， 并且所述控制输入被配置为当所述选择信号处于第一状态时从总线主机接收被配置为与第一从设备通信的选择信号;以及第二不同的从设备，当所述选择信号处于第二状态时 不同的状态

公开(公告)号：US20170132051A1

公开(公告)日：2017-05-11

申请号：US15412198

申请日：2017-01-23

Applicant: Atmel Corporation

Inventor： Frode Milch Pedersen ,  Sebastien Jouin ,  Stein Danielsen ,  Francois Fosse ,  Thierry Delalande ,  Ivar Holand ,  James Halliman

IPC: G06F9/52 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F9/526 ,  G06F11/00 ,  G06F11/004 ,  G06F13/122 ,  G06F13/28 ,  G06F13/362 ,  G06F13/4004 ,  G06F13/4282 ,  G06F17/30362 ,  G06F2201/825

Abstract: Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.

公开(公告)号：US09152598B2

公开(公告)日：2015-10-06

申请号：US13687044

申请日：2012-11-28

Applicant: Atmel Corporation

Inventor： Francois Fosse ,  Laurent Le Goffic

IPC: G06F13/00 ,  G06F13/42 ,  G06F13/364

CPC classification number: G06F13/4068 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4291 ,  G06F2213/0016

Abstract: A device comprising: a bus master, including a bi-directional data and clock lines, configured to produce a select signal output for enabling data transmission on the bi-directional data line to first/second different data busses supporting multiple slave devices configured to receive/transmit data over a respective data bus and to receive a clock signal from the bus master from the clock line; and a de-multiplexer including an input, first and second outputs and a control input, the input coupled to the bi-directional data line of the bus master, first/second outputs of the de-multiplexer coupled to first/second data busses, respectively, and the control input configured to receive the select signal from the bus master that is configured to communicate to a first slave device when the select signal is in a first state, and a second different slave device when the select signal is in a second different state.

Abstract translation: 一种设备，包括：总线主机，包括双向数据和时钟线，被配置为产生选择信号输出，用于使所述双向数据线上的数据传输能够支持第一/第二不同数据总线，所述数据总线支持被配置为接收的多个从设备 通过相应的数据总线发送数据，并从时钟线接收总线主机的时钟信号; 以及解复用器，包括输入，第一和第二输出和控制输入，耦合到总线主机的双向数据线的输入，耦合到第一/第二数据总线的解复用器的第一/第二输出， 并且所述控制输入被配置为当所述选择信号处于第一状态时从总线主机接收被配置为与第一从设备通信的选择信号;以及第二不同的从设备，当所述选择信号处于第二状态时 不同的状态