公开(公告)号：US20120195135A1

公开(公告)日：2012-08-02

申请号：US13243738

申请日：2011-09-23

申请人： Atsushi KAWASUMI

发明人： Atsushi KAWASUMI

IPC分类号： G11C7/10

CPC分类号： G11C11/413

摘要： According to one embodiment, a semiconductor memory device includes a plurality of memory cells each of which is arranged at the intersection position between a pair of complementary bit lines and a word line, and stores data between a first power supply voltage applied to a first node and a voltage applied to a virtual ground node, and a control circuit which changes the amount of current of the pair of bit lines in accordance with the amplitude of the pair of bit lines for each column in a memory macro, that is formed by arranging the plurality of memory cells in a matrix, in the data read operation of each of the plurality of memory cells.

摘要翻译： 根据一个实施例，半导体存储器件包括多个存储器单元，每个存储单元布置在一对互补位线和字线之间的交叉位置处，并且在施加到第一节点的第一电源电压之间存储数据 以及施加到虚拟接地节点的电压，以及控制电路，其根据存储器宏中每列的一对位线的幅度来改变一对位线的电流量，其通过布置 在多个存储单元中的每一个的数据读取操作中，矩阵中的多个存储单元。

公开(公告)号：US20100165771A1

公开(公告)日：2010-07-01

申请号：US12643925

申请日：2009-12-21

申请人： Atsushi KAWASUMI

发明人： Atsushi KAWASUMI

IPC分类号： G11C7/02

CPC分类号： G11C7/22 ,  G11C7/02 ,  G11C7/227

摘要： A semiconductor memory device comprises a plurality of word lines, a plurality of bit lines intersecting the word lines, a memory cell array having a plurality of memory cell each provided at an intersection of the word line and the bit line, a plurality of sense amplifier each of which detects and amplifies a signal level of the bit line, a replica word line, a replica bit line intersecting the replica word line, a replica memory cell provided at each intersection of the replica word line and the replica bit line, a replica circuit which simulates reading out of the memory cell, and a timing generating circuit which quantizes a replica delay time that is a time until the replica bit line changes from a reference timing, and which generates an activation timing for the sense amplifier based on a quantization result.

摘要翻译： 半导体存储器件包括多个字线，与字线相交的多个位线，存储单元阵列，具有分别设置在字线和位线的交点处的多个存储单元，多个读出放大器 每一个检测和放大位线的信号电平，复制字线，与副本字线相交的副本位线，在复制字线和副本位线的每个交叉点处提供的副本存储单元，复本 模拟从存储单元读出的电路，以及定时产生电路，其量化直到复制位线从参考定时改变为止的时间的复制延迟时间，并且其基于量化产生用于读出放大器的激活定时 结果。

公开(公告)号：US20130258782A1

公开(公告)日：2013-10-03

申请号：US13603666

申请日：2012-09-05

申请人： Kosuke TATSUMURA ,  Masato ODA ,  Koichiro ZAITSU ,  Atsushi KAWASUMI ,  Mari MATSUMOTO ,  Shinichi YASUDA

发明人： Kosuke TATSUMURA ,  Masato ODA ,  Koichiro ZAITSU ,  Atsushi KAWASUMI ,  Mari MATSUMOTO ,  Shinichi YASUDA

IPC分类号： G11C16/06

CPC分类号： G11C16/06 ,  G11C7/06 ,  G11C16/26

摘要： According to one embodiment, a configuration memory includes first and second data lines, a first memory string which comprises at least first and second nonvolatile memory transistors which are connected in series between a common node and the first data line, a second memory string which comprises at least third and fourth nonvolatile memory transistors which are connected in series between the common node and the second data line, and a flip-flop circuit which comprises a first data holding node connected to the common node and a second data holding node connected to a configuration data output node.

摘要翻译： 根据一个实施例，配置存储器包括第一和第二数据线，第一存储器串，其包括串联连接在公共节点和第一数据线之间的至少第一和第二非易失性存储器晶体管，第二存储器串包括 在公共节点和第二数据线之间串联连接的至少第三和第四非易失性存储器晶体管，以及包括连接到公共节点的第一数据保持节点和连接到公共节点的第二数据保持节点的触发器电路 配置数据输出节点。

公开(公告)号：US20130250659A1

公开(公告)日：2013-09-26

申请号：US13623329

申请日：2012-09-20

申请人： Atsushi KAWASUMI

发明人： Atsushi KAWASUMI

IPC分类号： G11C5/14 ,  G11C11/413

CPC分类号： G11C7/227 ,  G11C11/412 ,  G11C11/419

摘要： According to one embodiment, a semiconductor memory device includes a memory cell array including memory cells, word lines connected to the memory cell array to select rows of the memory cell array, first bit lines connected to the memory cell array to select columns of the memory cell array, a replica cell array including replica cells respectively connected to the word lines, and storing information on characteristics of the rows of the memory cell array, and a second bit line connected to the replica cells. An operation is changed for each row of the memory cell array based on the information in the replica cells.

摘要翻译： 根据一个实施例，半导体存储器件包括存储单元阵列，其包括存储器单元，连接到存储单元阵列的字线以选择存储单元阵列的行，连接到存储单元阵列的第一位线，以选择存储器的列 单元阵列，包括分别连接到字线的复制单元的副本单元阵列，以及存储关于存储单元阵列的行的特性的信息，以及连接到复制单元的第二位线。 基于复制单元中的信息，针对存储单元阵列的每行改变操作。

公开(公告)号：US20100046279A1

公开(公告)日：2010-02-25

申请号：US12539883

申请日：2009-08-12

申请人： Atsushi KAWASUMI ,  Yukihiro URAKAWA

发明人： Atsushi KAWASUMI ,  Yukihiro URAKAWA

IPC分类号： G11C11/00 ,  G11C5/14 ,  G11C7/02

CPC分类号： G11C7/02 ,  G11C5/147 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C29/02 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028 ,  G11C29/50 ,  G11C2207/2254

摘要： The first power supply terminal is connected to source electrodes of the first and third transistors. The second power supply terminal is connected to source electrodes of the second and fourth transistors.When offset information of the memory cell is to be read, a voltage applied to the first power supply terminal and a voltage applied to the second power supply terminal are made equal. Then the voltage applied to the first power supply terminal is returned to the first potential, and the voltage applied to the second power supply terminal is returned to the second potential. When stress is generated in the first to fourth transistor included in the first or second inverter, the potential difference between the first power supply terminal and the second power supply terminal is made larger than a difference between the first potential and the second potential.

摘要翻译： 第一电源端子连接到第一和第三晶体管的源电极。 第二电源端子连接到第二和第四晶体管的源电极。 当要读取存储器单元的偏移信息时，施加到第一电源端子的电压和施加到第二电源端子的电压相等。 然后，施加到第一电源端子的电压返回到第一电位，并且施加到第二电源端子的电压返回到第二电位。 当在包括在第一或第二逆变器中的第一至第四晶体管中产生应力时，使得第一电源端子和第二电源端子之间的电位差大于第一电位和第二电位之间的差。

公开(公告)号：US20070242499A1

公开(公告)日：2007-10-18

申请号：US11697059

申请日：2007-04-05

申请人： Atsushi KAWASUMI

发明人： Atsushi KAWASUMI

IPC分类号： G11C11/00

CPC分类号： G11C11/413

摘要： This disclosure concerns a LSI comprising two bit lines; two input nodes; sense nodes transmitting a signal difference input to the two input nodes; an output node outputting the amplified signal; a current adjustment gate adjusting an amount of current flowing through one of the two sense nodes; a latch circuit controlling the current adjustment gate; two signal lines transmitting a voltage source and a comparison voltage via the two input nodes, the comparison voltage being obtained by subtracting a predetermined threshold voltage from the power source voltage; and two switching elements provided between the two input nodes and the two signal lines, wherein the latch circuit switches the current adjustment gate in the case where the amplified signal is an inversion signal of an amplified signal according to the threshold voltage when the power source voltage and the comparison voltage are respectively applied to the two input nodes.

摘要翻译： 本公开涉及包含两个位线的LSI; 两个输入节点; 感测节点向两个输入节点发送信号差分输入; 输出所述放大信号的输出节点; 电流调节门调节流过两个感测节点中的一个的电流量; 控制电流调节门的锁存电路; 通过两个输入节点传送电压源和比较电压的两个信号线，所述比较电压通过从所述电源电压减去预定阈值电压而获得; 以及设置在两个输入节点和两条信号线之间的两个开关元件，其中当放大信号是放大信号的反相信号时，锁存电路根据阈值电压切换电流调节门，当电源电压 并将比较电压分别施加到两个输入节点。

公开(公告)号：US20130141959A1

公开(公告)日：2013-06-06

申请号：US13426443

申请日：2012-03-21

申请人： Atsushi KAWASUMI

发明人： Atsushi KAWASUMI

IPC分类号： G11C5/06

CPC分类号： G11C7/12 ,  G11C7/18 ,  G11C11/419

摘要： A semiconductor memory device according to an embodiment comprises: a plurality of memory cells arranged in a first direction and a second direction; local bit lines connected to group of the memory cells; a global bit line to be commonly connected to a plurality of the local bit lines; and switch circuits connected between the local bit lines and the global bit line. The switch circuits connect the global bit line to one of the local bit lines, the one of the local bit lines being electrically connected to the memory cells of the group located at a position specified by select information of the first direction and the second direction.

摘要翻译： 根据实施例的半导体存储器件包括：沿第一方向和第二方向布置的多个存储单元; 连接到存储单元组的局部位线; 通常连接到多个局部位线的全局位线; 以及连接在本地位线和全局位线之间的开关电路。 开关电路将全局位线连接到局部位线之一，局部位线之一电连接到位于由第一方向和第二方向的选择信息指定的位置处的组的存储单元。

公开(公告)号：US20100194398A1

公开(公告)日：2010-08-05

申请号：US12692841

申请日：2010-01-25

申请人： Atsushi KAWASUMI ,  Toru Nishikawa

发明人： Atsushi KAWASUMI ,  Toru Nishikawa

IPC分类号： G01N27/416

CPC分类号： H01M2/34 ,  H01M10/42 ,  Y10T307/516

摘要： The rechargeable battery abnormality detection apparatus is provided with an internal short circuit detection section (20b) that monitors rechargeable battery (1) voltage change when no charging or discharging takes place, and detects internal short circuit abnormality when battery voltage drop during a predetermined time period exceeds a preset threshold voltage; a degradation appraisal section (20d) that judges the degree of rechargeable battery degradation; and a threshold control section (20c) that incrementally increases the threshold voltage according to the degree of degradation determined by the degradation appraisal section (20d).

摘要翻译： 可再充电电池异常检测装置具有内部短路检测部（20b），其在不发生充电或放电的情况下监视可再充电电池（1）电压变化，并且在预定时间段期间当电池电压下降时检测内部短路异常 超过预设阈值电压; 评估可再充电电池劣化程度的劣化鉴别部分（20d）; 以及阈值控制部（20c），其根据由劣化鉴别部（20d）确定的劣化程度递增地增加阈值电压。

公开(公告)号：US20100165697A1

公开(公告)日：2010-07-01

申请号：US12645397

申请日：2009-12-22

申请人： Atsushi KAWASUMI

发明人： Atsushi KAWASUMI

IPC分类号： G11C5/06 ,  G11C8/08

CPC分类号： G11C11/412

摘要： A semiconductor storage device includes: a memory cell array including a plurality of first wirings, a plurality of second wirings intersecting with the first wirings, and a plurality of memory cells respectively arranged at intersections of the first and second wirings; a plurality of drivers that drive the first wirings; a dummy wiring continuously extending in a direction of the first wirings and in a direction of the second wirings, a part of the dummy wiring extending in the direction of the second wirings being connected to the plurality of drivers; a plurality of switch circuits connected to respective connection portions of the plurality of drivers and the dummy wiring; and a replica line extending in the direction of the second wirings and connected to the dummy wiring through the plurality of switch circuits.

摘要翻译： 半导体存储装置包括：存储单元阵列，包括多个第一布线，与第一布线相交的多个第二布线，以及分别布置在第一布线和第二布线的交点处的多个存储单元; 驱动第一布线的多个驱动器; 连接在第一配线的方向上并在第二配线的方向上延伸的虚拟配线，沿着第二配线的方向延伸的虚拟配线的一部分与多个驱动器连接; 连接到多个驱动器的相应连接部分和虚拟布线的多个开关电路; 以及沿着第二配线的方向延伸并通过多个开关电路连接到虚拟布线的复制线。

公开(公告)号：US20090168500A1

公开(公告)日：2009-07-02

申请号：US12343996

申请日：2008-12-24

申请人： Atsushi KAWASUMI

发明人： Atsushi KAWASUMI

IPC分类号： G11C11/00 ,  G11C11/416 ,  G11C7/00

CPC分类号： G11C11/416 ,  G11C7/12 ,  G11C7/18 ,  G11C11/412

摘要： A semiconductor memory device includes a sub array including a plurality of memory cells each holding data arranged therein; a memory cell array including a plurality of the sub arrays arranged therein; paired bit lines including a first bit line and a second bit line connected to each of the sub arrays; and a write/read circuit arranged to correspond to each of the sub arrays, writing data to the sub array, and reading data from the sub array, wherein a pair of the sub array and the write/read circuit is repeatedly arranged along the paired bit lines, allowing the data to be transferred via the write/read circuit and the paired bit lines,

摘要翻译： 半导体存储器件包括：子阵列，其包括多个存储单元，每个存储单元保持布置在其中的数据; 包括布置在其中的多个子阵列的存储单元阵列; 成对位线，包括连接到每个子阵列的第一位线和第二位线; 以及写入/读取电路，被布置为对应于每个子阵列，将数据写入子阵列，以及从子阵列读取数据，其中一对子阵列和写/读电路沿着配对重复排列 位线，允许数据通过写/读电路和配对位线传输，