公开(公告)号：US08601012B2

公开(公告)日：2013-12-03

申请号：US12737933

申请日：2008-09-11

申请人： Shinichi Yasuda ,  Koichi Abe ,  Shogo Tsubouchi

发明人： Shinichi Yasuda ,  Koichi Abe ,  Shogo Tsubouchi

IPC分类号： G06F17/30

CPC分类号： G06F17/30029 ,  G06F17/30038

摘要： An automatic search and transfer apparatus that automatically searches for and transfers data one or more computers connected via a network, that includes a keyword input section that inputs at least one keyword, a search section that searches for data including the at least one keyword and acquires attribute data of concerned data from the one or more computers connected via the network, a reporting section that reports information relating to the concerned data to a user, a reception section that receives the concerned data from one or more computers, and a data storage section that stores the data. The reporting section reports acquisition of the attribute data to the user when the attribute data is acquired, and the reception section starts reception of the concerned data after the reporting section has reported the acquisition of the attribute data of the concerned data to the user.

摘要翻译： 一种自动搜索和传送装置，其自动搜索和传送经由网络连接的一个或多个计算机的数据，其包括输入至少一个关键字的关键字输入部分，搜索包括至少一个关键字的数据的搜索部分，并获取 来自经由网络连接的一台以上的计算机的有关数据的属性数据，向用户报告与有关数据有关的信息的报告部，从一台以上的计算机接收有关数据的接收部，以及数据存储部 存储数据。 报告部分在获取属性数据时向用户报告属性数据的获取，并且在报告部分已经向用户报告了有关数据的属性数据的获取之后，接收部分开始接收相关数据。

公开(公告)号：US20130307054A1

公开(公告)日：2013-11-21

申请号：US13606292

申请日：2012-09-07

申请人： Shinichi YASUDA ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Koichiro Zaitsu ,  Masato Oda ,  Atsuhiro Kinoshita ,  Daisuke Hagishima ,  Yoshifumi Nishi ,  Takahiro Kurita ,  Shinobu Fujita

发明人： Shinichi YASUDA ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Koichiro Zaitsu ,  Masato Oda ,  Atsuhiro Kinoshita ,  Daisuke Hagishima ,  Yoshifumi Nishi ,  Takahiro Kurita ,  Shinobu Fujita

IPC分类号： H01L27/105

CPC分类号： G11C16/10 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/7881 ,  H01L29/792

摘要： One embodiment provides a semiconductor integrated circuit, including: a substrate; a plurality of nonvolatile memory portions formed in the substrate, each including a first nonvolatile memory and a second nonvolatile memory; and a plurality of logic transistor portions formed in the substrate, each including at least one of logic transistor, wherein the logic transistors include: a first transistor which is directly connected to drains of the first and second nonvolatile memories at its gate; and a second transistor which is not directly connected to the drains of the first and second nonvolatile memories, and wherein a bottom surface of the gate of each of the logic transistors sandwiching the first and second nonvolatile memories is lower in height from a top surface of the substrate than a bottom surface of the control gate of each of the first and second nonvolatile memories.

摘要翻译： 一个实施例提供一种半导体集成电路，包括：基板; 形成在所述基板中的多个非易失性存储部，每个包括第一非易失性存储器和第二非易失性存储器; 以及形成在所述衬底中的多个逻辑晶体管部分，每个逻辑晶体管部分包括逻辑晶体管中的至少一个，其中所述逻辑晶体管包括：第一晶体管，其第一和第二非易失性存储器的栅极直接连接到第一晶体管; 以及第二晶体管，其不直接连接到第一和第二非易失性存储器的漏极，并且其中夹着第一和第二非易失性存储器的每个逻辑晶体管的栅极的底表面的高度与 所述基板比所述第一和第二非易失性存储器中的每一个的所述控制栅极的底表面。

公开(公告)号：US20130258782A1

公开(公告)日：2013-10-03

申请号：US13603666

申请日：2012-09-05

申请人： Kosuke TATSUMURA ,  Masato ODA ,  Koichiro ZAITSU ,  Atsushi KAWASUMI ,  Mari MATSUMOTO ,  Shinichi YASUDA

发明人： Kosuke TATSUMURA ,  Masato ODA ,  Koichiro ZAITSU ,  Atsushi KAWASUMI ,  Mari MATSUMOTO ,  Shinichi YASUDA

IPC分类号： G11C16/06

CPC分类号： G11C16/06 ,  G11C7/06 ,  G11C16/26

摘要： According to one embodiment, a configuration memory includes first and second data lines, a first memory string which comprises at least first and second nonvolatile memory transistors which are connected in series between a common node and the first data line, a second memory string which comprises at least third and fourth nonvolatile memory transistors which are connected in series between the common node and the second data line, and a flip-flop circuit which comprises a first data holding node connected to the common node and a second data holding node connected to a configuration data output node.

摘要翻译： 根据一个实施例，配置存储器包括第一和第二数据线，第一存储器串，其包括串联连接在公共节点和第一数据线之间的至少第一和第二非易失性存储器晶体管，第二存储器串包括 在公共节点和第二数据线之间串联连接的至少第三和第四非易失性存储器晶体管，以及包括连接到公共节点的第一数据保持节点和连接到公共节点的第二数据保持节点的触发器电路 配置数据输出节点。

公开(公告)号：US08307022B2

公开(公告)日：2012-11-06

申请号：US12130567

申请日：2008-05-30

申请人： Mari Matsumoto ,  Ryuji Ohba ,  Shinichi Yasuda ,  Shinobu Fujita

发明人： Mari Matsumoto ,  Ryuji Ohba ,  Shinichi Yasuda ,  Shinobu Fujita

IPC分类号： G06F1/02

CPC分类号： G06F7/588 ,  H03K3/84

摘要： A random number generating device includes: a pulse voltage generator configured to generate a pulse voltage having an amplitude of 26 mV or more; a random noise generating element including source and drain regions formed at a distance from each other on a semiconductor substrate, a tunnel insulating film formed on a portion of the semiconductor substrate located between the source region and the drain region, and a gate electrode formed above the tunnel insulating film and to which the pulse voltage is applied, the random noise generating element configured to generate a random noise contained in a current flowing between the source region and the drain region; and a random number generating unit configured to generate a random number signal based on the random noise.

摘要翻译： 随机数生成装置包括：脉冲电压发生器，被配置为产生具有26mV或更大幅度的脉冲电压; 包括形成在半导体衬底上彼此间隔一定距离的源极和漏极区域的随机噪声产生元件，形成在位于源极区域和漏极区域之间的半导体衬底的一部分上的隧道绝缘膜以及形成在栅极电极上的栅电极 隧道绝缘膜，并且施加脉冲电压，所述随机噪声产生元件被配置为产生包含在源极区域和漏极区域之间的电流中的随机噪声; 以及随机数生成单元，被配置为基于随机噪声生成随机数信号。

公开(公告)号：US20120243336A1

公开(公告)日：2012-09-27

申请号：US13240087

申请日：2011-09-22

申请人： Yoshifumi NISHI ,  Daisuke HAGISHIMA ,  Shinichi YASUDA ,  Tetsufumi TANAMOTO ,  Takahiro KURITA ,  Atsuhiro KINOSHITA ,  Shinobu FUJITA

发明人： Yoshifumi NISHI ,  Daisuke HAGISHIMA ,  Shinichi YASUDA ,  Tetsufumi TANAMOTO ,  Takahiro KURITA ,  Atsuhiro KINOSHITA ,  Shinobu FUJITA

IPC分类号： G11C16/10 ,  H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0458 ,  G11C16/10 ,  H01L27/11573 ,  H01L27/11803

摘要： An aspect of the present embodiment, there is provided a nonvolatile programmable logic switch including a first memory cell transistor, a second memory cell transistor, a pass transistor and a first substrate electrode applying a substrate voltage to the pass transistor, wherein a writing voltage is applied to the first wiring, a first voltage is applied to one of a second wiring and a third wiring and a second voltage which is lower than the first voltage is applied to the other of the second wiring and the third wiring, and the first substrate voltage which is higher than the second voltage and lower than the first voltage is applied to a well of the pass transistor, when data is written into the first memory cell transistor or the second memory cell transistor.

摘要翻译： 本实施例的一个方面提供了一种非易失性可编程逻辑开关，包括第一存储单元晶体管，第二存储单元晶体管，传输晶体管和向该通过晶体管施加衬底电压的第一衬底电极，其中写入电压为 施加到第一布线，第一电压施加到第二布线和第三布线中的一个，并且低于第一电压的第二电压施加到第二布线和第三布线中的另一布线，第一基板 当数据被写入第一存储单元晶体管或第二存储单元晶体管时，高于第二电压并低于第一电压的电压被施加到传输晶体管的阱。

公开(公告)号：US20110205780A1

公开(公告)日：2011-08-25

申请号：US12880758

申请日：2010-09-13

申请人： Shinichi Yasuda ,  Keiko Abe ,  Shinobu Fujita

发明人： Shinichi Yasuda ,  Keiko Abe ,  Shinobu Fujita

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/75 ,  H03K19/17728 ,  H03K19/1776

摘要： In one embodiment, a semiconductor integrated circuit includes a first resistive-change element, a second resistive-change element and a first switching element. The first resistive-change element includes one end having a first polarity connected to a first power source. The first resistive-change element includes another end having a second polarity connected to an output node. The second resistive-change element includes one end having the second polarity connected to the output node. The first switching element includes a first terminal connected to another end of the second resistive-change element. The first switching element includes a second terminal connected to a second power source.

摘要翻译： 在一个实施例中，半导体集成电路包括第一电阻变化元件，第二电阻变化元件和第一开关元件。 第一电阻变化元件包括具有连接到第一电源的第一极性的一端。 第一电阻变化元件包括具有连接到输出节点的第二极性的另一端。 第二电阻变化元件包括具有连接到输出节点的第二极性的一端。 第一开关元件包括连接到第二电阻变化元件的另一端的第一端子。 第一开关元件包括连接到第二电源的第二端子。

公开(公告)号：US07795920B2

公开(公告)日：2010-09-14

申请号：US12367379

申请日：2009-02-06

申请人： Shinichi Yasuda

发明人： Shinichi Yasuda

IPC分类号： H03K19/00

CPC分类号： G01R31/31725 ,  G01R31/31727

摘要： A semiconductor integrated circuit includes a flipflop holding and outputting input data according to a clock, the flipflop having: an input end to which data is input; an output end from which data is output; a first logic gate connected between the input end and the output end, the first logic gate operating according to the clock; a second logic gate connected between the first logic gate and the output end, the second logic gate operating according to the clock; and a buffer circuit. An input of the buffer circuit is connected to a node between the first logic gate and the input end. An output of the buffer circuit is connected to a node in an output side of the first logic gate. The buffer circuit transitions according to an enable signal from a high impedance state to a state in which a signal can be transmitted.

摘要翻译： 一种半导体集成电路包括触发器，其保持并根据时钟输出输入数据，所述触发器具有：输入数据的输入端; 输出数据的输出端; 连接在输入端和输出端之间的第一逻辑门，第一逻辑门根据时钟工作; 连接在第一逻辑门和输出端之间的第二逻辑门，第二逻辑门根据时钟工作; 和缓冲电路。 缓冲电路的输入连接到第一逻辑门和输入端之间的节点。 缓冲电路的输出连接到第一逻辑门的输出侧的节点。 缓冲电路根据从高阻抗状态的使能信号转换到可以发送信号的状态。

公开(公告)号：US20090249141A1

公开(公告)日：2009-10-01

申请号：US12367379

申请日：2009-02-06

申请人： Shinichi YASUDA

发明人： Shinichi YASUDA

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/31725 ,  G01R31/31727

摘要： A semiconductor integrated circuit includes a flipflop holding and outputting input data according to a clock, the flipflop having: an input end to which data is input; an output end from which data is output; a first logic gate connected between the input end and the output end, the first logic gate operating according to the clock; a second logic gate connected between the first logic gate and the output end, the second logic gate operating according to the clock; and a buffer circuit. An input of the buffer circuit is connected to a node between the first logic gate and the input end. An output of the buffer circuit is connected to a node in an output side of the first logic gate. The buffer circuit transitions according to an enable signal from a high impedance state to a state in which a signal can be transmitted.

摘要翻译： 一种半导体集成电路包括触发器，其保持并根据时钟输出输入数据，所述触发器具有：输入数据的输入端; 输出数据的输出端; 连接在输入端和输出端之间的第一逻辑门，第一逻辑门根据时钟工作; 连接在第一逻辑门和输出端之间的第二逻辑门，第二逻辑门根据时钟工作; 和缓冲电路。 缓冲电路的输入连接到第一逻辑门和输入端之间的节点。 缓冲电路的输出连接到第一逻辑门的输出侧的节点。 缓冲电路根据从高阻抗状态的使能信号转换到可以发送信号的状态。

公开(公告)号：US07392271B2

公开(公告)日：2008-06-24

申请号：US10919291

申请日：2004-08-17

申请人： Shinichi Yasuda ,  Shinobu Fujita

发明人： Shinichi Yasuda ,  Shinobu Fujita

IPC分类号： G06F1/02

CPC分类号： G06F7/58

摘要： A random number generating circuit receives as input a first digital random number signal generated at a first generating rate and produces as output a second digital random number signal having a second generating rate that is twice as high as the first generating rate. A semiconductor integrated circuit, an IC card and an information terminal device comprising the random number circuit is provided.

摘要翻译： 随机数产生电路接收以第一产生速率产生的第一数字随机数信号作为输出，产生第二数字随机数信号，该第二数字随机数信号的第二发生速率是第一发生速率的两倍。 提供了包括随机数电路的半导体集成电路，IC卡和信息终端装置。

公开(公告)号：US07184297B2

公开(公告)日：2007-02-27

申请号：US11165404

申请日：2005-06-24

申请人： Shinichi Yasuda ,  Keiko Abe

发明人： Shinichi Yasuda ,  Keiko Abe

IPC分类号： G11C11/00 ,  G11C27/00 ,  G11C5/06 ,  G11C11/34

CPC分类号： G11C11/14

摘要： A semiconductor memory includes: a first node and a second node; a first MIS transistor, having first conductive carrier flows, including a source electrode connected to a first power supply, a drain electrode connected to the second node, and a gate electrode connected to the first node; a second MIS transistor, having second conductive carrier flows, including a source electrode connected to a second power supply, a drain electrode connected to the second node, and a gate electrode connected to the first node; and a resistance change element connected between the first node and the second node and having a variable resistance due to the direction in which a voltage is applied, wherein information is written in the resistance change element by applying a voltage between the first and the second node, and stored information is read out by applying a low or high input voltage to the first node and reading out a voltage difference in the second node.

摘要翻译： 半导体存储器包括：第一节点和第二节点; 具有第一导电载流子的第一MIS晶体管，包括连接到第一电源的源电极，连接到第二节点的漏电极和连接到第一节点的栅电极; 具有第二导电载流子的第二MIS晶体管，包括连接到第二电源的源电极，连接到第二节点的漏电极和连接到第一节点的栅电极; 以及连接在第一节点和第二节点之间并且由于施加电压的方向而具有可变电阻的电阻变化元件，其中通过在第一和第二节点之间施加电压将信息写入电阻变化元件 并且通过向第一节点施加低或高输入电压并读出第二节点中的电压差来读出存储的信息。