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公开(公告)号：US11683048B2
公开(公告)日：2023-06-20
申请号：US17236328
申请日：2021-04-21
发明人： Ahmed Elkholy , Yousr Ismail , Adesh Garg , Ali Nazemi , Jun Cao
CPC分类号： H03M3/50 , H03L7/0991 , H03L7/00 , H03L7/087 , H03L7/197 , H03L7/1976
摘要： Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.
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公开(公告)号：US20240039483A1
公开(公告)日：2024-02-01
申请号：US17877157
申请日：2022-07-29
发明人： Yousr Ismail , Adesh Garg
IPC分类号： H03F1/48
CPC分类号： H03F1/483
摘要： A circuit for inductive peaking may include a driver, an inverter, a resistor between an output node of the driver and an input node of the inverter and a switch. For example, a first node of the resistor may be connected to the output node of the driver and a second node of the resistor may be connected to the input node of the inverter. The switch may be connected between an output node of the inverter and the first node of the resistor. An input node of the driver may correspond to an input node of the circuit and the output node of the driver may correspond to an output node of the circuit.
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公开(公告)号：US20230268929A1
公开(公告)日：2023-08-24
申请号：US18310737
申请日：2023-05-02
发明人： Ahmed Elkholy , Yousr Ismail , Adesh Garg , Ali Nazemi , Jun Cao
CPC分类号： H03M3/50 , H03L7/0991 , H03L7/197
摘要： Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.
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公开(公告)号：US20220345152A1
公开(公告)日：2022-10-27
申请号：US17236328
申请日：2021-04-21
发明人： Ahmed Elkholy , Yousr Ismail , Adesh Garg , Ali Nazemi , Jun Cao
摘要： Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.
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