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公开(公告)号：US20210356856A1
公开(公告)日：2021-11-18
申请号：US16343756
申请日：2018-10-26
发明人： Xiaoxiang ZHANG , Mingxuan LIU , Huibin GUO , Yongzhi SONG , Xiaolong LI , Wenqing XU , Zumou WU
IPC分类号： G03F1/32 , H01L21/027
摘要： A phase shift mask includes a transparent substrate and light-shielding portions. The light-shielding portions include a first light-shielding portion, and over one side of it, a first compensating light-shielding portion, which has a first distance to the first light-shielding portion and a first width smaller than a resolution of an exposing machine utilized for an exposure process using the phase shift mask. The light-shielding portions can further include a second compensating light-shielding portion, having a second distance to another side of the first light-shielding portion and a second width smaller than the resolution of the exposing machine. The first distance and the second distance respectively allow the first and the second compensating light-shielding portion to reduce an exposure at a region corresponding to two sides of the first light-shielding portion during the exposure process. A method manufacturing an electronic component utilizing the phase shift mask is also provided.
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公开(公告)号：US20190043898A1
公开(公告)日：2019-02-07
申请号：US15544562
申请日：2017-01-11
发明人： Jing WANG , Huibin GUO , Xiangqian DING , Jinchao BAI , Yao LIU
IPC分类号： H01L27/12 , H01L21/027 , G02F1/1362 , G02F1/1368 , G02F1/1343 , G03F7/039 , G03F7/16 , G03F7/20 , G03F7/32 , G03F7/038
摘要： An array substrate motherboard, a manufacturing method thereof and a display device are provided. The manufacturing method includes forming a film layer pattern for a first display product at a first region of a base substrate and forming a film layer pattern for a second display product at a second region of the base substrate. The first display product has deep holes at a density larger than the second display product, and each deep hole is a via-hole penetrating through at least two insulation layers. Specifically, the manufacturing method include: prior to forming a second conductive pattern on an insulation layer, reducing a thickness of the insulation layer at the first region; and forming the second conductive pattern on the insulation layer, and enabling the second conductive pattern to be connected to a first conductive pattern under the insulation layer through a via-hole structure penetrating through the insulation layer.
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公开(公告)号：US20180364530A1
公开(公告)日：2018-12-20
申请号：US15521339
申请日：2016-11-02
发明人： Shoukun WANG , Liangliang LI , Yuchun FENG , Huibin GUO
IPC分类号： G02F1/1362 , G02F1/1368 , H01L27/12
CPC分类号： G02F1/136209 , G02F1/136204 , G02F1/136286 , G02F1/1368 , G02F2001/136231 , G02F2202/22 , H01L27/1262 , H01L27/1288
摘要： This present disclosure provides an array substrate, a manufacturing method thereof, and a display apparatus, aiming at solving the issue of light reflection on the array substrates and improving the display effects of display apparatuses. The array substrate includes a transparent substrate; a plurality of components disposed on a first side of the transparent substrate; and a shielding pattern, disposed on a second side of the transparent substrate, and configured to shield light reflected from a surface of at least one of the plurality of components.
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公开(公告)号：US20170269445A1
公开(公告)日：2017-09-21
申请号：US15505376
申请日：2016-08-29
发明人： Jinchao BAI , Huibin GUO , Yao LIU , Xiangqian DING
IPC分类号： G02F1/1362 , G02F1/1343 , G02F1/1368
CPC分类号： G02F1/136227 , G02F1/133345 , G02F1/13439 , G02F1/136286 , G02F1/1368 , G02F2001/136236 , G02F2201/121 , G02F2201/123 , H01L21/77 , H01L27/12
摘要： An array substrate and a manufacturing method thereof, a display panel and a display device are disclosed. The method for manufacturing an array substrate includes: forming a first via hole (11) for connecting a second transparent electrically conductive layer (39) and a gate line layer (39), a second via hole (12) for connecting a first transparent electrically conductive layer (30) and the second transparent electrically conductive layer (39), and a third via hole (13) for connecting the second transparent electrically conductive layer (39) and a source/drain electrode layer (34) on a base substrate (10) through patterning process; performing a filling process on the first via hole (11), the second via hole (12) and the third via hole (13) during a pattern of second transparent electrically conductive layer is being formed, such that each of the first via hole, the second via hole and the third via hole which are filled has a top surface which is in the same horizontal plane as portions of the second transparent electrically conductive layer (39) surrounding the respective via holes. The method can reduce the height difference between the top surface of the via hole and the transparent electrically conductive layer surrounding the via hole and to solve the problem of uneven diffusion of the PI orientation layer.
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公开(公告)号：US20150329432A1
公开(公告)日：2015-11-19
申请号：US14526777
申请日：2014-10-29
发明人： Liangliang LI , Zongjie GUO , Huibin GUO , Shoukun WANG , Yuchun FENG , Xiaowei LIU
CPC分类号： H01L21/02691 , C04B41/0036 , C04B41/0072 , C04B41/5353 , C04B41/91 , H01L21/02422 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/02686
摘要： Disclosed is a method for preparing a polycrystalline metal oxide pattern, characterized by comprising: annealing a predetermined region of an amorphous metal oxide film by laser, so as to convert the amorphous metal oxide in the predetermined region into a polycrystalline metal oxide; and etching the amorphous metal oxide outside of the predetermined region so as to remove it. By the method according to the present invention, firstly, the predetermined region of an amorphous metal oxide film is annealed by laser so as to convert the amorphous metal oxide into a polycrystalline metal oxide, and then, the amorphous metal oxide outside of the predetermined region is etched away, thereby a polycrystalline metal oxide pattern is formed. The method for preparing a polycrystalline metal oxide pattern according to the present invention is simple, and can effectively shorten the production period and save production costs.
摘要翻译： 公开了一种制备多晶金属氧化物图案的方法，其特征在于包括：通过激光对预定区域的非晶金属氧化物膜进行退火，以将预定区域中的非晶态金属氧化物转化成多晶金属氧化物; 并且在预定区域外蚀刻非晶态金属氧化物以便将其去除。 根据本发明的方法，首先，通过激光对非晶金属氧化物膜的预定区域进行退火，以将非晶金属氧化物转化为多晶金属氧化物，然后在预定区域外部的非晶态金属氧化物 被蚀刻掉，从而形成多晶金属氧化物图案。 根据本发明的多晶金属氧化物图案的制备方法简单，可以有效缩短生产周期，节省生产成本。
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公开(公告)号：US20190103419A1
公开(公告)日：2019-04-04
申请号：US16028017
申请日：2018-07-05
发明人： Shoukun WANG , Huibin GUO , Hao HAN , Fangbin FU , Yongzhi SONG
IPC分类号： H01L27/12 , G02F1/1368
摘要： An array substrate, a manufacturing method thereof, and a display apparatus are provided. The array substrate includes a display area and a non-display area in the periphery of the display area, the display area includes pixel regions, the display and non-display areas are provided with via holes, wherein each pixel region is provided, at a side facing a display side, with a reflection layer configured to reflect light irradiated thereon from an external light source to form a display image; and an anti-deterioration layer in contact with the reflection layer is provided in the via holes in the display and non-display areas. Thus, by using a new material, utilization of external light source is improved without additional masking process, and connection in via holes in the display area, and especially in the non-display area is achieved, which prevents deterioration of the via holes and poor contact resistance.
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7.发明申请公开(公告)号：US20180203281A1
公开(公告)日：2018-07-19
申请号：US15541580
申请日：2017-01-03
发明人： Xiaoxiang ZHANG , Liping LUO , Mingxuan LIU , Huibin GUO , Zhichao ZHANG
IPC分类号： G02F1/1343 , G02B5/20 , G02F1/1362 , G02F1/1335 , H01L51/52 , H01L27/32
CPC分类号： G02F1/13439 , G02B5/201 , G02F1/133345 , G02F1/133502 , G02F1/133514 , G02F1/133553 , G02F1/1362 , G02F1/136286 , G02F2001/136295 , G02F2201/38 , H01L27/12 , H01L27/3244 , H01L51/0096 , H01L51/5268 , H01L51/5284 , Y02E10/549
摘要： A manufacturing method of a metal layer, a functional substrate and a manufacturing method thereof, and a display device are provided. The manufacturing method of a metal layer includes: forming an insulating layer on a base substrate; forming an etching buffer layer on the insulating layer; patterning the etching buffer layer and the insulating layer to form a plurality of recessed microstructures in the insulating layer; stripping the etching buffer layer; and forming a metal layer on the insulating layer, a surface of the metal layer adjacent to the insulating layer is formed with a plurality of protruded portions which are filled into the plurality of recessed microstructures. The manufacturing method of a metal layer may form a metal layer with anti-reflection effect.
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公开(公告)号：US20180090377A1
公开(公告)日：2018-03-29
申请号：US15521079
申请日：2016-09-07
发明人： Shoukun WANG , Huibin GUO , Yuchun FENG , Liangliang LI
IPC分类号： H01L21/77 , H01L21/3213 , H01L27/14
CPC分类号： H01L21/77 , H01L21/32139 , H01L27/12 , H01L27/124 , H01L27/1259 , H01L27/14
摘要： An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate, a signal line disposed on the base substrate, an extinction layer disposed between the base substrate and the signal line, the extinction layer being configured to reduce an ambient light when the array substrate is located on a light exiting side. An orthographic projection of the signal line in a plane of the base substrate is coincided with an orthographic projection of the extinction layer in the plane of the base substrate.
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公开(公告)号：US20150348999A1
公开(公告)日：2015-12-03
申请号：US14519480
申请日：2014-10-21
发明人： Huibin GUO , Shoukun WANG , Xiaowei LIU , Yuchun FENG , Zongjie GUO
CPC分类号： H01L27/1262 , H01L27/1288 , H01L29/458 , H01L29/4908
摘要： Provided is a manufacturing method of an array substrate with an etching stop layer. The method includes: forming a pattern including a gate, a gate line and a common electrode line on a substrate through a first patterning process; forming a gate insulation layer, an active layer film and an etching stop layer through a second patterning process; wherein, the etching stop layer corresponds to a gap between a source and a drain which are to be formed, and a via hole exposing the common electrode line is formed above the common electrode line; forming at least an active layer, a pattern including source, drain and data line and a protection layer through a third patterning process; wherein, the protection layer exposes a part of the drain; and forming at least a pixel electrode through a fourth patterning process; wherein, the pixel electrode is electrically connected with the drain.
摘要翻译： 提供了具有蚀刻停止层的阵列基板的制造方法。 该方法包括：通过第一图案化工艺在衬底上形成包括栅极，栅极线和公共电极线的图案; 通过第二图案化工艺形成栅极绝缘层，有源层膜和蚀刻停止层; 其中，所述蚀刻停止层对应于要形成的源极和漏极之间的间隙，并且在所述公共电极线上方形成暴露所述公共电极线的通孔; 通过第三图案化工艺形成至少有源层，包括源极，漏极和数据线的图案和保护层; 其中，所述保护层暴露所述漏极的一部分; 以及通过第四图案化工艺形成至少一个像素电极; 其中，像素电极与漏极电连接。
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公开(公告)号：US20210210527A1
公开(公告)日：2021-07-08
申请号：US16074185
申请日：2017-12-14
发明人： Jinchao BAI , Xiao HAN , Qi SANG , Huibin GUO , Yongzhi SONG
IPC分类号： H01L27/12 , G02F1/1362 , G02F1/1343 , G02F1/1335
摘要： A method for manufacturing an array substrate, including forming a thin film transistor and a peripheral circuit; forming a passivation layer covering at least the thin film transistor and the peripheral circuit; forming a first via hole penetrating the passivation layer and exposing part of a drain of the thin film transistor, and a second via hole penetrating the passivation layer and exposing part of the peripheral circuit; forming a first conductive layer pattern on the passivation layer, the first conductive layer pattern covering the first via hole and the second via hole; forming a reflective metal layer pattern and a second conductive layer pattern on the first conductive layer pattern, the second conductive layer pattern covering the second via hole.
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