ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE
    3.
    发明申请
    ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE 有权
    阵列基板及其制造方法,显示装置

    公开(公告)号:US20160254289A1

    公开(公告)日:2016-09-01

    申请号:US14436843

    申请日:2014-09-11

    IPC分类号: H01L27/12

    摘要: An array substrate and manufacturing method thereof and display device are provided. The method of manufacturing the array substrate includes forming a pattern including a gate electrode, a gate line, a common electrode line and a gate insulating layer on a substrate; forming a pattern including a data line, a source electrode, a drain electrode and an active layer; forming a pattern including an insulating interlayer over the pattern of the source electrode, the drain electrode and the active layer; forming a pattern including a first transparent electrode over the insulating interlayer; forming a pattern including a passivation layer over the first transparent electrode; and forming a pattern including a second transparent electrode over the passivation layer. The method can efficiently prevent the ITO process polluting the TFT channel.

    摘要翻译: 提供阵列基板及其制造方法和显示装置。 制造阵列基板的方法包括在基板上形成包括栅极,栅极线,公共电极线和栅极绝缘层的图案; 形成包括数据线,源电极,漏电极和有源层的图案; 在源电极,漏电极和有源层的图案上形成包括绝缘中间层的图案; 在所述绝缘中间层上形成包括第一透明电极的图案; 在所述第一透明电极上形成包括钝化层的图案; 以及在所述钝化层上形成包括第二透明电极的图案。 该方法可以有效地防止ITO工艺污染TFT通道。

    METHOD FOR MANUFACTURING FAN-OUT LINES ON ARRAY SUBSTRATE
    6.
    发明申请
    METHOD FOR MANUFACTURING FAN-OUT LINES ON ARRAY SUBSTRATE 有权
    在阵列基板上制造扇形线的方法

    公开(公告)号:US20140134809A1

    公开(公告)日:2014-05-15

    申请号:US14077770

    申请日:2013-11-12

    IPC分类号: H01L27/12

    摘要: A method for manufacturing fan-out lines on an array substrate is disclosed. The fan-out lines comprise an amorphous silicon layer, an ohmic contact layer and a source-drain electrode layer disposed on a gate insulating layer. The manufacturing processes can be conducted by forming a first layer of photoresist on the source-drain electrode layer and performing a half-exposure development process on the first layer of photoresist; etching the amorphous silicon layer, the ohmic contact layer and the source-drain electrode layer by an etching process; removing the first layer of photoresist; foiming a second layer of photoresist and performing full-exposure development process on the second layer of photoresist; and etching the amorphous silicon layer by etching process to form the fan-out lines.

    摘要翻译: 公开了一种在阵列基板上制造扇出线的方法。 扇出线包括非晶硅层,欧姆接触层和设置在栅极绝缘层上的源极 - 漏极电极层。 可以通过在源极 - 漏极电极层上形成第一层光致抗蚀剂并在第一层光致抗蚀剂上进行半曝光显影处理来进行制造工艺; 通过蚀刻工艺蚀刻非晶硅层,欧姆接触层和源极 - 漏极电极层; 去除第一层光刻胶; 在第二层光致抗蚀剂上形成第二层光致抗蚀剂并进行全曝光显影处理; 并通过蚀刻工艺蚀刻非晶硅层以形成扇出线。

    Dry Etching Method
    10.
    发明申请
    Dry Etching Method 有权
    干法蚀刻法

    公开(公告)号:US20150311039A1

    公开(公告)日:2015-10-29

    申请号:US14447915

    申请日:2014-07-31

    IPC分类号: H01J37/32

    摘要: The present invention discloses a dry etching method. The dry etching method comprises: etching a first medium layer; introducing a second reaction gas in a reaction chamber, and exciting the second reaction gas into plasmas with a second radiofrequency power, so that the plasmas formed from the second reaction gas are combined with particulate pollutants in the reaction chamber, and in this case the reaction chamber is vacuumized to perform conversion processing; and etching a second medium layer. The technical solution of the present invention is capable of effectively preventing particulate pollutants from falling onto the glass substrate in the procedure of executing conversion processing, meanwhile, the effect of chamber purifying through vacuumizing is improved, and the amount of the particulate pollutants in the reaction chamber is effectively reduced.

    摘要翻译: 本发明公开了一种干式蚀刻方法。 干蚀刻方法包括:蚀刻第一介质层; 在反应室中引入第二反应气体,并以第二射频功率将第二反应气体激发成等离子体,使得由第二反应气体形成的等离子体与反应室中的颗粒污染物组合,在这种情况下反应 真空室进行转化处理; 并蚀刻第二介质层。 本发明的技术方案在执行转化处理的过程中能够有效地防止颗粒污染物落入玻璃基板上,同时通过真空度提高室内净化的效果,反应中颗粒污染物的量 室被有效地减少。