METHOD FOR FABRICATING DISPLAYING BASE PLATE, DISPLAYING BASE PLATE AND DISPLAYING DEVICE

    公开(公告)号:US20220059728A1

    公开(公告)日:2022-02-24

    申请号:US17340672

    申请日:2021-06-07

    IPC分类号: H01L33/48 H01L25/075

    摘要: A displaying base plate and a fabricating method thereof. The displaying base plate includes a substrate, and a first flat layer on one side of the substrate; a first metal layer on one side of the first flat layer that is further away from the substrate; a second flat layer on sides of the first metal layer and the first flat layer that are further away from the substrate; and a second metal layer on one side of the second flat layer that is further away from the substrate; wherein the first metal layer includes a first metal trace, an orthographic projection of the second metal layer on the substrate and an orthographic projection of the first metal trace on the substrate have an overlapping part, and an orthographic projection of the second flat layer on the substrate covers the orthographic projection of the first metal trace on the substrate.

    Display Substrate and Display Apparatus
    4.
    发明公开

    公开(公告)号:US20240276775A1

    公开(公告)日:2024-08-15

    申请号:US18023381

    申请日:2022-03-16

    IPC分类号: H10K59/122 H10K59/35

    CPC分类号: H10K59/122 H10K59/35

    摘要: A display substrate includes a light emitting structure layer arranged on a base substrate, the light emitting structure layer includes a first electrode layer, a pixel definition layer, a light emitting functional layer, a second electrode layer, a third electrode layer and an electrode insulation layer; the first electrode layer includes multiple first electrodes, and the pixel definition layer is provided with a pixel opening exposing a first electrode and a grid-shaped isolation groove structure; the third electrode layer and the electrode insulation layer are sequentially stacked on a side of the pixel definition layer; the light emitting functional layer and the second electrode layer are sequentially stacked; the second electrode layer and the third electrode layer are configured to be equipotential; the light emitting functional layer includes at least two stacked light emitting units and a charge generation layer positioned between two adjacent light emitting units.

    PIXEL COMPENSATION CIRCUIT AND MANUFACTURING METHOD THEREOF, OLED ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

    公开(公告)号:US20210265439A1

    公开(公告)日:2021-08-26

    申请号:US17255866

    申请日:2020-04-10

    IPC分类号: H01L27/32

    摘要: The present disclosure provides a pixel compensation circuit and a manufacturing method thereof, an OLED array substrate and a manufacturing method thereof, and a display device. The pixel compensation circuit includes a first TFT and a second TFT on a substrate. The first TFT includes: a first electrode on the substrate, a first interlayer dielectric layer on a side of the first electrode away from the substrate and having an opening exposing at least a portion of the first electrode; a second electrode on a side of the first interlayer dielectric layer away from the first electrode; and an active layer extending from the second electrode to the first electrode. The second TFT includes: an active layer on the substrate; and a first electrode and a second electrode in a same layer and on a side of the active layer of the second TFT away from the substrate.

    DISPLAY PANEL, METHOD FOR MANUFACTURING THE SAME, AND TILED SCREEN

    公开(公告)号:US20230013848A1

    公开(公告)日:2023-01-19

    申请号:US17783207

    申请日:2021-05-20

    IPC分类号: H01L27/32

    摘要: A display panel has a display region and a fan-out lead region, the fan-out lead region is located within the display region. The display panel comprises a base, a pixel circuit layer, a plurality of fan-out leads disposed between the base and the pixel circuit layer and located in the fan-out lead region, and an electrical field shielding pattern disposed between the pixel circuit layer and a film layer in which the plurality of fan-out leads are located. The pixel circuit layer includes a plurality of pixel circuits, at least one pixel circuit is located in the fan-out lead region. At least one fan-out lead is electrically connected to the pixel circuits. Orthographic projection of active layer patterns of transistors of the pixel circuit located in the fan-out lead region on the base are located within an orthographic projection of the electric field shielding pattern on the base.