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公开(公告)号：US20200242996A1
公开(公告)日：2020-07-30
申请号：US16714385
申请日：2019-12-13
Inventor： Zhen WANG , Han ZHANG , Zhengkui WANG , Wei YAN , Yun QIAO , Wenwen QIN , Xiaozhou ZHAN , Jian SUN , Jian ZHANG , Deshuai WANG
IPC: G09G3/20
Abstract: A display panel, a display device and a display control method thereof are provided in the present disclosure. The display panel includes: a time division multiplexing multiplexer (MUX) signal input circuit, which is connected with each of the plurality of signal lines, and configured to input data signals of each frame of display image to the plurality of signal lines, and for each frame of display image, input trigger signals corresponding to sub-pixel units of different colors to the plurality of signal lines in a time-sharing manner; among the plurality of signal lines, electrical signals on a plurality of adjacent first signal lines are arranged in sequence according to an order of positive, positive, negative and negative; among the plurality of signal lines, a first signal line has a spacing distance from adjacent signal lines less than a preset value.
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公开(公告)号：US20250166542A1
公开(公告)日：2025-05-22
申请号：US19023209
申请日：2025-01-15
Applicant: BOE Technology Group Co., Ltd.
Inventor： Wei YAN , Zhen WANG , Wenwen QIN , Han ZHANG , Deshuai WANG , Jian ZHANG , Yue SHAN , Xiaoyan YANG , Yadong ZHANG , Jian SUN
Abstract: A shift register and a driving method therefor, a gate driving circuit and a display device are provided, wherein the shift register includes a pull-up control sub-circuit configured to provide a signal of a first signal terminal or a second signal terminal to a pull-up control node under control of a first input terminal and a second output terminal; the pull-down control sub-circuit is configured to provide a signal of a first power supply terminal or a second power supply terminal to a pull-down node under control of the pull-up control node, the first signal terminal, the second signal terminal, a first clock signal terminal and a second clock signal terminal; the output sub-circuit is configured to supply a signal of a third clock signal terminal to a first output terminal and a signal of a fourth clock signal terminal to the second output terminal.
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公开(公告)号：US20250157396A1
公开(公告)日：2025-05-15
申请号：US19021203
申请日：2025-01-15
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jian ZHANG , Zhen WANG , Deshuai WANG , Han ZHANG , Wei YAN , Jian SUN
IPC: G09G3/32
Abstract: A display substrate and a display apparatus are provided. The display substrate includes a base substrate; sub-pixels arranged in an array and on the base substrate; data line groups on the base substrate; each data line group includes data lines, each of which is connected to one column of sub-pixels; data selectors on the base substrate and connected to the data line groups in a one-to-one correspondence; data lines in a same data line group are connected to a same data selector; and data selection signal lines, wherein different data selection signal lines output different data selection signals; and different data lines connected to a same data selector correspond to different data selection signal lines, respectively. The display panel provided may effectively reduce the resistance on the data selection signal lines, thereby reducing the delay of the data selection signals and further improving the charging uniformity of sub-pixels.
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公开(公告)号：US20230395008A1
公开(公告)日：2023-12-07
申请号：US18032512
申请日：2020-10-21
Applicant: BOE Technology Group Co., Ltd.
Inventor： Wei YAN , Wenwen QIN , Yue SHAN , Deshuai WANG , Jiguo WANG , Zhen WANG , Xiaoyan YANG , Han ZHANG , Jian ZHANG , Yadong ZHANG , Jian SUN
CPC classification number: G09G3/20 , G11C19/28 , G09G2310/0286
Abstract: A shift register unit, a driving method, a drive circuit, and a display apparatus are disclosed. The shift register unit includes: a control circuit, which is configured to adjust signals of a first node and a second node according to an input signal end, a first control signal end, a second control signal end and a first reference signal end; a cascade circuit, which is configured to provide, according to the signal of the first node, a signal of a first cascade clock signal end to a cascade output end; and an output circuit, which is configured to provide, according to the signal of the first node, a signal of a control clock signal end to a drive output end, and provide, according to the signal of the second node, a signal of a second reference signal end to the drive output end.
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公开(公告)号：US20230154933A1
公开(公告)日：2023-05-18
申请号：US17622708
申请日：2021-01-29
Applicant: BOE Technology Group Co., Ltd.
Inventor： Jiguo WANG , Jian SUN , Zhao ZHANG , Liang TIAN , Weida QIN , Zhen WANG , Han ZHANG , Wenwen QIN , Xiaoyan YANG , Yue SHAN , Wei YAN , Jian ZHANG , Deshuai WANG , Yadong ZHANG , Jiantao LIU
IPC: H01L27/12 , G02F1/1362 , G02F1/1368
CPC classification number: H01L27/124 , G02F1/13629 , G02F1/136213 , H01L27/1255 , G02F1/1368 , G02F1/136209 , G02F1/136222
Abstract: An array substrate includes: a first substrate (10), including a plurality of sub-pixel regions (101) arranged in an array along a row direction (X) and a column direction (Y); a pixel circuit layer, including a plurality of sub-pixel circuits; a planarization layer (17), provided with a first via hole (170) located in the sub-pixel regions (101), and includes at least one pattern portion (171), the pattern portion (171) includes a plurality of pattern units (171a) arranged in an array along the row direction (X) and the column direction (Y); and a reflective electrode layer, wherein the reflective electrode layer includes a plurality of reflective electrodes (18) that are mutually disconnected, each of the reflective electrodes (18) is located in one of the sub-pixel regions (101) and is electrically connected to the sub-pixel circuit through the first via hole (170).
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Patent Agency Ranking
公开(公告)号：US20250078772A1
公开(公告)日：2025-03-06
申请号：US18563532
申请日：2022-06-30
Inventor： Peirong HUO , Changcheng LIU , Jingyi XU , Chao LIANG , Zhenhong XIAO , Peng LIU , Wei YAN , Jiantao LIU , Bo LI , Hong LIU
Abstract: The present disclosure provides a gate driving circuit and a display panel. The display panel includes a display area and a peripheral area surrounding the display area. At least one gate driving circuit is arranged in the peripheral area. The at least one gate driving circuit includes a plurality of shift register units cascaded in sequence. The plurality of shift register units include first shift register units and second shift register units. The first shift register units and the second shift register units are spaced apart from each other. The number of transistors in the first shift register units is smaller than the number of transistors in the second shift register units.
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公开(公告)号：US20230040448A1
公开(公告)日：2023-02-09
申请号：US17789768
申请日：2021-08-18
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jian ZHANG , Zhen WANG , Deshuai WANG , Han ZHANG , Wei YAN , Jian SUN
IPC: G09G3/32
Abstract: A display substrate and a display apparatus are provided. The display substrate includes a base substrate; sub-pixels arranged in an array and on the base substrate; data line groups on the base substrate; each data line group includes data lines, each of which is connected to one column of sub-pixels; data selectors on the base substrate and connected to the data line groups in a one-to-one correspondence; data lines in a same data line group are connected to a same data selector; and a data selection signal lines, wherein different data selection signal lines output different data selection signals; and different data lines connected to a same data selector correspond to different data selection signal lines, respectively. The display panel provided may effectively reduce the resistance on the data selection signal lines, thereby reducing the delay of the data selection signals and further improving the charging uniformity of sub-pixels.
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公开(公告)号：US20220317535A1
公开(公告)日：2022-10-06
申请号：US17427622
申请日：2020-10-22
Applicant: BOE Technology Group Co., Ltd.
Inventor： Jian ZHANG , Zhen WANG , Deshuai WANG , Han ZHANG , Wei YAN , Jian SUN
IPC: G02F1/1362
Abstract: The present disclosure provides an array substrate, a manufacturing method thereof and a display device. The array substrate includes: a display area and a peripheral area surrounding the display area; the display area is provided with a plurality of gate lines and a plurality of data lines, the gate lines and the data lines are crossed to define a plurality of sub-pixel regions distributed in an array; a first electrode, the first electrode including a first portion located in the display area and a second portion located in the peripheral area; an electrode connection line, the electrode connection line is located in the peripheral area, the electrode connection line is electrically connected to the second portion; a plurality of compensation signal lines, at least part of the compensation signal lines are located in the display area, and the compensation signal lines are electrically connected to the first portion.
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公开(公告)号：US20220276528A1
公开(公告)日：2022-09-01
申请号：US17509080
申请日：2021-10-25
Applicant: BOE Technology Group Co., Ltd.
Inventor： Zhao ZHANG , Yanqing CHEN , Wei LI , Weida QIN , Kai CHEN , Jiguo WANG , Wei YAN , Xiaofeng ZHANG , Zeliang LI , Jian ZHANG , Zhen WANG
IPC: G02F1/1335 , G02F1/1362 , G02F1/1341
Abstract: Provided are a display panel, a preparation method thereof, and a display apparatus. The display panel includes a first substrate and a second substrate disposed oppositely, and a liquid crystal layer sandwiched between the first substrate and the second substrate, wherein the first substrate includes a black matrix layer and a color filter layer which are sequentially disposed on a first base substrate; at least one of the first substrate and the second substrate further includes a spacer; and the black matrix layer includes at least one first black matrix, and an orthographic projection of each first black matrix on the first base substrate covers an orthographic projection of the spacer on the first base substrate.
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公开(公告)号：US20240105112A1
公开(公告)日：2024-03-28
申请号：US18519614
申请日：2023-11-27
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Jian ZHANG , Zhen WANG , Deshuai WANG , Han ZHANG , Wei YAN , Jian SUN
IPC: G09G3/32
CPC classification number: G09G3/32 , G09G2310/0275 , G09G2310/0297 , G09G2310/08
Abstract: A display substrate and a display apparatus are provided. The display substrate includes a base substrate; sub-pixels arranged in an array and on the base substrate; data line groups on the base substrate; each data line group includes data lines, each of which is connected to one column of sub-pixels; data selectors on the base substrate and connected to the data line groups in a one-to-one correspondence; data lines in a same data line group are connected to a same data selector; and data selection signal lines, wherein different data selection signal lines output different data selection signals; and different data lines connected to a same data selector correspond to different data selection signal lines, respectively. The display panel provided may effectively reduce the resistance on the data selection signal lines, thereby reducing the delay of the data selection signals and further improving the charging uniformity of sub-pixels.
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