公开(公告)号：US3775844A

公开(公告)日：1973-12-04

申请号：US3775844D

申请日：1972-04-27

Applicant: BUNKER RAMO

Inventor： PARKS H

IPC: H01L21/60 ,  H01L23/538 ,  H05K3/30 ,  H05K13/00

CPC classification number: H01L23/5385 ,  H01L24/81 ,  H01L2224/81801 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3025 ,  Y10T29/49123 ,  Y10T29/49126

Abstract: A method of fabricating an electrical circuit structure comprised of a plurality of electrically conductive wafers stacked together under pressure to form a parallelpiped structure containing one or more active components (e.g., integrated circuit chips) as well as conductor means providing coaxial interconnections in X, Y and Z-axis directions. A stack is normally comprised of conductive wafers of different types including component wafers, interconnection wafers, and connector wafers. Z-axis interconnections, i.e., through-connections in a wafer, are fabricated directly from the wafer material itself by selective chemical etching of the wafer so as to form spaced electrically insulated solid conductive slugs within the wafer profile extending between the top and bottom wafer surfaces, with each slug being surrounded by dielectric material which supports the slug and electrically isolates it from the remainder of the wafer material. X-Y axis interconnections for electrically connecting the Z-axis slugs in a wafer in a predetermined manner are also fabricated directly from the wafer material by selective chemical etching so as to form X-Y axis conductors which are likewise contained within the wafer profile and surrounded by dielectric material providing support and electrical isolation. Highly reliable wafer-to-wafer electrical interconnections are obtained in a stack by providing malleable conductive contacts between opposing contacting Z-axis slugs in adjacent wafers, and pressure stacking the wafers so that these malleable contacts are deformed. Additional malleable contacts which are likewise deformed by the pressure stacking are also advantageously provided between other opposing portions of adjacent wafer surfaces for providing wafer-to-wafer ground interconnections. The advantages of pressure stacking are further increased by providing a uniform pattern for the Z-axis slugs and the ground interconnections on all of the wafers of a stack so as to obtain uniform distribution.

公开(公告)号：US3813773A

公开(公告)日：1974-06-04

申请号：US28616372

申请日：1972-09-05

Applicant: BUNKER RAMO

Inventor： PARKS H

IPC: H05K3/36 ,  H01L23/04 ,  H05K1/16 ,  H05K3/04 ,  H05K3/06 ,  H05K3/10 ,  H05K3/44 ,  H05K3/46 ,  H01R9/00

CPC classification number: H05K3/445 ,  H05K3/041 ,  H05K3/06 ,  H05K3/107 ,  H05K3/4614 ,  H05K2201/096 ,  H05K2201/09745 ,  H05K2201/09881 ,  H05K2203/0323 ,  H05K2203/0369 ,  Y10T29/49126 ,  Y10T29/49155

Abstract: A low-cost method employing precision stamping for fabricating the wafers of a multiwafer electrical circuit structure comprised of a plurality of electrically conductive wafers stacked together under pressure. A stack is normally comprised of conductive wafers of different types including component wafers, interconnection wafers, and connector wafers which are fabricated to provide X, Y and Z-axis coaxial connections between components in the stack. In accordance with the present invention, these X, Y and Z coaxial connections are fabricated directly from the wafer material itself at relatively low cost as compared to known methods as a result of the employment of a novel combination of precision stamping, dielectric filling and sanding or etching steps.

Abstract translation: 一种采用精密冲压的低成本方法，用于制造由在压力下堆叠在一起的多个导电晶片组成的多晶圆电路结构的晶片。 堆叠通常由不同类型的导电晶片组成，包括组件晶片，互连晶片和连接器晶片，其被制造为在堆叠中的组件之间提供X，Y和Z轴同轴连接。 根据本发明，与已知方法相比，这些X，Y和Z同轴连接直接从晶片材料本身以相对较低的成本制造，因为采用精密冲压，电介质填充和打磨的新颖组合 或蚀刻步骤。

公开(公告)号：US3708874A

公开(公告)日：1973-01-09

申请号：US3708874D

申请日：1971-08-23

Applicant: BUNKER RAMO

Inventor： PARKS H

IPC: G11C11/04 ,  H01F7/06

CPC classification number: G11C11/04 ,  Y10T29/49069

Abstract: A magnetic wire memory construction comprising a plurality of stacked memory planes, each memory plane being formed from two like-formed self-supporting and rigid metal sheets in opposed relation. The sheets have channels formed therein using precision batch fabricated metal sculpturing techniques, with certain of the channels being filled with insulative material. The dimensions and locations of the channels are chosen so that precisely located memory wire receiving tunnels and corresponding insulated drive line strips perpendicular thereto are formed when the sheets are placed together in opposed relation. Memory wire elements are inserted into the tunnels which protect and shield the elements and maintain them accurately positioned with respect to one another and to the drive line strips so as to permit achieving a memory of increased density and speed of operation.

Abstract translation: 一种磁线存储器结构，包括多个堆叠的存储器平面，每个存储器平面由相对关系的两个相似形状的自支撑和刚性金属板形成。 这些片材具有使用精密批量制造的金属雕刻技术形成的通道，其中一些通道​​填充有绝缘材料。 选择通道的尺寸和位置，使得当片材以相对的关系放置在一起时，形成精确定位的存储器线接收隧道和垂直于其的相应的绝缘驱动线条。 存储器线元件被插入到隧道中，这些隧道保护和屏蔽元件并将它们相对于彼此和驱动线条精确地定位，以便实现增加密度和操作速度的记忆。