公开(公告)号：US20240155778A1

公开(公告)日：2024-05-09

申请号：US18502605

申请日：2023-11-06

申请人： SHINKO ELECTRIC INDUSTRIES CO., LTD.

发明人： Akihiro Takeuchi

IPC分类号： H05K3/46

CPC分类号： H05K3/4688 ,  H05K2201/0212 ,  H05K2203/0369

摘要： A wiring substrate includes a metal layer, a resin layer, and a wiring structure. The resin layer is laminated on the metal layer. The wiring structure includes a wiring layer and an insulating layer that are laminated on the resin layer, and in which the wiring layer is located by being brought into contact with the resin layer.

公开(公告)号：US20240107685A1

公开(公告)日：2024-03-28

申请号：US18475288

申请日：2023-09-27

申请人： IBIDEN CO., LTD.

发明人： Susumu KAGOHASHI ,  Jun SAKAI ,  Kyohei YOSHIKAWA ,  Takuya INISHI

IPC分类号： H05K3/46 ,  H05K1/03 ,  H05K1/11 ,  H05K3/06 ,  H05K3/16

CPC分类号： H05K3/4688 ,  H05K1/0306 ,  H05K1/0313 ,  H05K1/116 ,  H05K3/062 ,  H05K3/16 ,  H05K3/4608 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0338 ,  H05K2203/0369

摘要： A printed wiring board includes a first conductor layer, a resin insulating layer having an opening, a second conductor layer including a seed layer and an electrolytic plating layer formed on the seed layer, and a via conductor including the seed layer and the electrolytic plating layer and connecting the first conductor and second conductor layers. The seed layer has a first portion on the surface of the insulating layer, a second portion on an inner wall surface in the opening of the insulating layer, and a third portion on a portion of the first conductor layer exposed by the opening of the insulating layer such that the first portion is thicker than the second portion and the third portion, the second portion has a first film and a second film electrically connected to the first film, and a portion of the first film is formed on the second film.

公开(公告)号：US09900996B2

公开(公告)日：2018-02-20

申请号：US14453977

申请日：2014-08-07

申请人： Siliconware Precision Industries Co., Ltd.

发明人： Chang-Fu Lin ,  Chin-Tsai Yao ,  Ming-Chin Chuang ,  Ko-Cheng Liu ,  Fu-Tang Huang

IPC分类号： H05K1/00 ,  H05K3/46 ,  H05K1/09 ,  H05K1/18 ,  H05K1/02 ,  H05K3/28

CPC分类号： H05K3/4644 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/181 ,  H05K1/02 ,  H05K1/0296 ,  H05K1/0298 ,  H05K1/181 ,  H05K3/284 ,  H05K2201/0191 ,  H05K2201/09736 ,  H05K2201/20 ,  H05K2203/0353 ,  H05K2203/0369 ,  H01L2924/00012 ,  H01L2924/00

摘要： A package substrate is provided, which includes a plurality of dielectric layers and a plurality of circuit layers alternately stacked with the dielectric layers. At least two of the circuit layers have a difference in thickness so as to prevent warpage of the substrate.

公开(公告)号：US09894764B2

公开(公告)日：2018-02-13

申请号：US15096993

申请日：2016-04-12

申请人： Samsung Electro-Mechanics Co., Ltd.

发明人： Sung-Uk Lee ,  Il-Jong Seo ,  Jae-Hoon Choi ,  Yong-Ho Baek

IPC分类号： H05K1/11 ,  H05K3/06

CPC分类号： H05K1/115 ,  H05K3/067 ,  H05K3/4647 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0361 ,  H05K2201/09854 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K2203/0384

摘要： A printed circuit board and a method of manufacturing a printed circuit board are provided. The printed circuit board includes an insulating layer, a circuit layer embedded in the insulating layer, a solder resist layer disposed on one surface of the insulating layer, the solder resist layer having a cavity of a through-hole shape to expose a part of the circuit layer from the insulating layer, and a metal post embedded in the solder resist layer and exposed to outside via an opening of the solder resist layer, and the metal post includes a first post metal layer, a post barrier layer, and a second post metal layer disposed in that order.

公开(公告)号：US09661761B2

公开(公告)日：2017-05-23

申请号：US13965194

申请日：2013-08-13

申请人： Unimicron Technology Corp.

发明人： Chun-Ting Lin

IPC分类号： H05K3/46 ,  H05K3/40 ,  H05K3/06 ,  H01L23/00

CPC分类号： H05K3/40 ,  H01L21/67265 ,  H01L21/673 ,  H01L21/67346 ,  H01L21/67763 ,  H01L21/6779 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/12042 ,  H05K1/11 ,  H05K3/06 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0979 ,  H05K2203/0369 ,  H05K2203/0376 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/00

摘要： A carrier substrate includes an insulation layer, conductive towers and a circuit structure layer. A diameter of each of the conductive towers is increased gradually from a top surface to a bottom surface, and the conductive towers include first conductive towers and second conductive towers surrounding the first conductive towers. The circuit structure layer is disposed on the insulation layer and includes at least one dielectric layer, at least two circuit layers and first conductive vias. Each of the second conductive towers correspondingly connects to at least two of the first conductive vias, and each of the first conductive towers correspondingly connects to one of the first conductive vias. An interface exists between the first conductive vias and the first and the second conductive towers.

公开(公告)号：US20160044792A1

公开(公告)日：2016-02-11

申请号：US14922972

申请日：2015-10-26

申请人： Shinko Electric Industries Co., Ltd.

发明人： Kentaro KANEKO ,  Toshimitsu Omiya ,  Kotaro Kodani ,  Junichi Nakamura ,  Kazuhiro Kobayashi

IPC分类号： H05K3/18 ,  H05K3/46 ,  C25D5/02 ,  H05K3/00

CPC分类号： H05K3/188 ,  C25D5/022 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/544 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K1/113 ,  H05K3/0017 ,  H05K3/46 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K2203/06 ,  Y10T29/49155 ,  H01L2924/00

摘要： A wiring substrate includes an insulating layer, a connection pad buried in the insulating layer in a state that an upper surface of the connection pad is exposed from an upper surface of the insulating layer and a lower surface and at least a part of a side surface of the connection pad contact the insulating layer, and a concave level difference portion formed in the insulating layer around an outer periphery part of the connection pad, wherein an upper surface of the connection pad and an upper surface of the insulating layer are arranged at a same height.

公开(公告)号：US20150382469A1

公开(公告)日：2015-12-31

申请号：US14492716

申请日：2014-09-22

申请人： PHOENIX PIONEER TECHNOLOGY CO., LTD.

发明人： Chu-Chin HU ,  Shih-Ping HSU ,  E-Tung CHOU

IPC分类号： H05K1/18 ,  H05K3/40 ,  H05K3/28 ,  H05K1/14 ,  H05K3/34

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/00 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/115 ,  H05K1/187 ,  H05K1/188 ,  H05K3/0014 ,  H05K3/0017 ,  H05K3/007 ,  H05K3/16 ,  H05K3/181 ,  H05K3/284 ,  H05K3/421 ,  H05K2201/0162 ,  H05K2201/0209 ,  H05K2201/09118 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/09636 ,  H05K2201/09854 ,  H05K2203/025 ,  H05K2203/0369 ,  H05K2203/0723 ,  H05K2203/0733 ,  H05K2203/1316 ,  H05K2203/1461 ,  H05K2203/1469 ,  H01L2924/00012 ,  H01L2224/81

摘要： A package apparatus comprises a first wiring layer, a first conductive pillar layer, a first molding compound layer, a second wiring layer, and a protection layer. The first wiring layer has a first surface and a second surface that are arranged opposite to each other. The first conductive pillar layer is disposed on the second surface of the first wiring layer, whereas the first conductive pillar layer is a non-circular conductive pillar layer. The first molding compound layer is disposed within a specific portion of the first wiring layer and the first conductive pillar layer. The second wiring layer is disposed on the first molding compound layer and one end of the first conductive pillar layer. The protection layer is disposed on the first molding compound layer and the second wiring layer.

摘要翻译： 包装装置包括第一布线层，第一导电柱层，第一模塑料层，第二布线层和保护层。 第一布线层具有彼此相对布置的第一表面和第二表面。 第一导电柱层设置在第一布线层的第二表面上，而第一导电柱层是非圆形导电柱层。 第一模塑料层设置在第一布线层和第一导电柱层的特定部分内。 第二布线层设置在第一模塑料层和第一导电柱层的一端。 保护层设置在第一模塑料层和第二布线层上。

公开(公告)号：US20150173185A1

公开(公告)日：2015-06-18

申请号：US14635429

申请日：2015-03-02

申请人： Murata Manufacturing Co., Ltd.

发明人： Satoshi Ito ,  Yoichi Moriya ,  Tetsuo Kanamori ,  Yukihiro Yagi ,  Yuki Yamamoto

IPC分类号： H05K1/02 ,  H05K3/46 ,  H05K3/06 ,  H05K1/11

CPC分类号： H05K1/0298 ,  H05K1/115 ,  H05K3/06 ,  H05K3/38 ,  H05K3/4038 ,  H05K3/4661 ,  H05K2201/0338 ,  H05K2201/0355 ,  H05K2201/09563 ,  H05K2203/0369 ,  H05K2203/0554 ,  H05K2203/063 ,  H05K2203/1105 ,  H05K2203/1461

摘要： A circuit board structure and a manufacturing method for a circuit board that ensures an electrical connection between a metal foil and a projection without using a conductive adhesive and is less likely to cause a decrease in the reliability of the connection due to the interlayer separation or the like is provided. A circuit board includes an insulating layer, a lower main surface wiring pattern and an upper main surface wiring pattern disposed on either side of the insulating layer, and an interlayer connection conductor passing through the insulating layer in a thickness direction and electrically connecting to the lower main surface wiring pattern and the upper main surface wiring pattern. The interlayer connection conductor is formed integrally with the lower main surface wiring pattern, and is bonded to the upper main surface wiring pattern via an intermetallic compound.

摘要翻译： 一种用于电路板的电路板结构和制造方法，其确保金属箔和突起之间的电连接而不使用导电粘合剂，并且不太可能导致由于层间隔离引起的连接的可靠性降低 喜欢被提供。 电路板包括绝缘层，下主表面布线图案和布置在绝缘层两侧的上主表面布线图案，以及层间连接导体，其沿​​厚度方向穿过绝缘层并电连接到下层 主表面布线图案和上表面布线图案。 层间连接导体与下主表面布线图形一体地形成，并且通过金属间化合物结合到上主表面布线图案。

公开(公告)号：US20140332252A1

公开(公告)日：2014-11-13

申请号：US13965194

申请日：2013-08-13

申请人： Unimicron Technology Corp.

发明人： Chun-Ting Lin

IPC分类号： H05K1/11 ,  H05K3/40

CPC分类号： H05K3/40 ,  H01L21/67265 ,  H01L21/673 ,  H01L21/67346 ,  H01L21/67763 ,  H01L21/6779 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/12042 ,  H05K1/11 ,  H05K3/06 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0979 ,  H05K2203/0369 ,  H05K2203/0376 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/00

摘要： A carrier substrate includes an insulation layer, conductive towers and a circuit structure layer. A diameter of each of the conductive towers is increased gradually from a top surface to a bottom surface, and the conductive towers include first conductive towers and second conductive towers surrounding the first conductive towers. The circuit structure layer is disposed on the insulation layer and includes at least one dielectric layer, at least two circuit layers and first conductive vias. Each of the second conductive towers correspondingly connects to at least two of the first conductive vias, and each of the first conductive towers correspondingly connects to one of the first conductive vias. An interface exists between the first conductive vias and the first and the second conductive towers.

摘要翻译： 载体基板包括绝缘层，导电塔和电路结构层。 每个导电塔的直径从顶表面逐渐增加到底表面，并且导电塔包括第一导电塔和围绕第一导电塔的第二导电塔。 电路结构层设置在绝缘层上，并且包括至少一个电介质层，至少两个电路层和第一导电通孔。 每个第二导电塔对应地连接到第一导电通孔中的至少两个，并且每个第一导电塔对应地连接到第一导电通孔之一。 在第一导电通孔和第一和第二导电塔之间存在界面。

公开(公告)号：US08828247B2

公开(公告)日：2014-09-09

申请号：US13589635

申请日：2012-08-20

申请人： Soon Chul Kwon ,  Sang Min Lee

发明人： Soon Chul Kwon ,  Sang Min Lee

IPC分类号： H01B13/00

CPC分类号： H05K3/045 ,  H05K3/4038 ,  H05K2203/025 ,  H05K2203/0323 ,  H05K2203/0369 ,  H05K2203/1476

摘要： Provided is a method of manufacturing a circuit which includes: (a) providing a substrate made of a conductive material; (b) etching a first surface of the substrate excluding a region in which at least one via is to be formed; (c) etching a region of the etched first surface of the substrate in which an insulated portion of a first circuit is to be formed; (d) stacking a first insulation layer in spaces formed by the etching performed in operations (b) and (c); and (e) grinding a second surface of the substrate to expose the first insulation layer outward along with the first circuit, thereby forming a circuit board.

摘要翻译： 提供一种制造电路的方法，包括：（a）提供由导电材料制成的基板; （b）蚀刻除了要形成至少一个通孔的区域之外的衬底的第一表面; （c）蚀刻要在其中形成第一电路的绝缘部分的所述衬底的蚀刻的第一表面的区域; （d）在操作（b）和（c）中执行的蚀刻形成的空间中堆叠第一绝缘层; 以及（e）研磨所述基板的第二表面以将所述第一绝缘层与所述第一电路一起向外露出，由此形成电路板。