-
公开(公告)号：US20110215827A1
公开(公告)日：2011-09-08
申请号：US12716341
申请日：2010-03-03
申请人： Baker S. Mohammad , Hong S. Kim , Paul D. Bassett
发明人： Baker S. Mohammad , Hong S. Kim , Paul D. Bassett
IPC分类号： G01R31/26
CPC分类号： G01R31/2642 , G11C11/41 , G11C29/12 , G11C29/50
摘要： In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.
摘要翻译： 在特定实施例中，一种方法包括在耦合到半导体器件的控制器处接收测试激活信号。 该方法还包括响应于所接收的测试激活信号来偏置半导体器件的至少一个晶体管的阱。 该偏压由对控制器作出响应的偏置电路提供。 当井被偏置时，执行半导体器件的测试以产生测试数据。
-
公开(公告)号：US08466707B2
公开(公告)日：2013-06-18
申请号：US12716341
申请日：2010-03-03
IPC分类号： G01R31/02
CPC分类号： G01R31/2642 , G11C11/41 , G11C29/12 , G11C29/50
摘要： In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.
摘要翻译： 在特定实施例中，一种方法包括在耦合到半导体器件的控制器处接收测试激活信号。 该方法还包括响应于所接收的测试激活信号来偏置半导体器件的至少一个晶体管的阱。 该偏压由对控制器作出响应的偏置电路提供。 当井被偏置时，执行半导体器件的测试以产生测试数据。
-
公开(公告)号：US07131034B2
公开(公告)日：2006-10-31
申请号：US10292329
申请日：2002-11-12
申请人： Nadeem N. Eleyan , Harsh D. Sharma , Howard L. Levy , Hong S. Kim
发明人： Nadeem N. Eleyan , Harsh D. Sharma , Howard L. Levy , Hong S. Kim
IPC分类号： G06F11/00
CPC分类号： G01R31/31725 , H03K5/26 , H03K2005/00058 , H03K2005/00156
摘要： A signal duration measurement system compares a known duration, T1, of a test data signal with the duration, T2, of a state of a signal under test. In one embodiment, if T2 compares favorably with T1, then the circuit generating the signal under test ‘passes.’ Otherwise the signal under test ‘fails,’ and a problem has been identified. Furthermore, in one embodiment, T1 can be selectively adjusted to more accurately measure T2. In one embodiment, the test data signal is allowed to travel a signal path, having a known signal propagation delay time, during a single state of the signal under test. The data signal at the beginning of the state, e.g. during the rise of the signal under test, is compared to the data signal captured at the end of the state, e.g. during the fall of the signal under test. If the initial and captured data signals are the same, then the duration of the state of the signal under test is greater than or equal to the signal propagation delay time. The signal propagation time can be adjusted by inserting varying delay elements into the signal path traversed by test data signal. The signal duration measurement system can be fabricated on-chip, thus making its use more practical. The signal duration measurement system is, for example, useful for measuring the state duration of signals such as self-resetting signals, which are difficult to externally measure.
摘要翻译： 信号持续时间测量系统将测试数据信号的已知持续时间T 1与被测信号的状态的持续时间T 2进行比较。 在一个实施例中，如果T 2与T 1相比较好，则产生被测信号的电路“通过”。 否则被测信号“失败”，并且已经确定了一个问题。 此外，在一个实施例中，可以选择性地调整T 1以更准确地测量T 2。在一个实施例中，允许测试数据信号在信号的单个状态期间行进具有已知信号传播延迟时间的信号路径 被测试。 状态开始时的数据信号，例如， 在被测信号的上升期间，与在状态结束时捕获的数据信号进行比较。 在被测信号的坠落期间。 如果初始和捕获的数据信号相同，则被测信号的持续时间大于或等于信号传播延迟时间。 可以通过将变化的延迟元件插入由测试数据信号穿过的信号路径来调节信号传播时间。 信号持续时间测量系统可以片上制造，从而使其使用更加实用。 信号持续时间测量系统例如可用于测量难以外部测量的诸如自复位信号的信号的状态持续时间。
-
公开(公告)号：US5636167A
公开(公告)日：1997-06-03
申请号：US679948
申请日：1996-07-15
申请人： Ki Y. Lee , Hong S. Kim
发明人： Ki Y. Lee , Hong S. Kim
CPC分类号： G11C29/24
摘要： Disclosed are redundancy row/column pretest circuits for a semiconductor memory device. Each of the redundancy row/column pretest circuits comprises a redundancy test pad for supplying a redundancy test signal, and a circuit for generating a normal row or column disable signal in response to the redundancy test signal from the redundancy test pad to disable a normal operation and perform a redundancy operation. Therefore, redundancy row/column cells are operated even under the condition that a redundancy circuit is not programmed, so that faults of the redundancy row/column cells can be tested in the same manner as those of normal cells.
摘要翻译： 公开了用于半导体存储器件的冗余行/列预测试电路。 冗余行/列预测试电路中的每一个包括用于提供冗余测试信号的冗余测试焊盘，以及用于响应于冗余测试板的冗余测试信号产生正常行或列禁止信号的电路，以禁用正常操作 并执行冗余操作。 因此，即使在冗余电路未编程的情况下，冗余行/列单元也被操作，从而可以以与正常单元相同的方式测试冗余行/列单元的故障。
-
公开(公告)号：US20120072791A1
公开(公告)日：2012-03-22
申请号：US12886629
申请日：2010-09-21
CPC分类号： G06F11/3656
摘要： A method and apparatus for performing a memory dump. The method includes providing a memory location from a debugger to a memory array through a BIST wrapper, and receiving data by the debugger read from the memory location in the memory array. The method can include sending a dump enable signal from the debugger, and the BIST wrapper selectively providing the memory location to the memory array in response to the dump enable signal. The method can include sending the dump enable signal to a multiplexer coupled to a register in the BIST wrapper, the dump enable signal causing the multiplexer to load the register with the memory location. The method can include asynchronously sending a write disable signal to the memory array before reading the data from the memory location. The received data can be selected from a larger set of data read from the memory location.
摘要翻译： 一种用于执行存储器转储的方法和装置。 该方法包括通过BIST包装器从调试器提供存储器位置到存储器阵列，以及通过从存储器阵列中的存储器位置读取的调试器接收数据。 该方法可以包括从调试器发送转储使能信号，并且BIST封装器响应于转储使能信号而选择性地将存储器位置提供给存储器阵列。 该方法可以包括将转储使能信号发送到耦合到BIST封装中的寄存器的多路复用器，转储使能信号使多路复用器将存储器位置加载寄存器。 该方法可以在从存储器位置读取数据之前异步地向存储器阵列发送写禁止信号。 所接收的数据可以从从存储器位置读取的更大数据集中选择。
-
公开(公告)号：US20110231719A1
公开(公告)日：2011-09-22
申请号：US12724527
申请日：2010-03-16
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318544 , G01R31/318533 , G01R31/318555
摘要： In a particular embodiment, a method is disclosed that includes mapping failing bit positions within multiple scan chains to memory locations of a memory mask. The method also includes executing logic built-in self-test (LBIST) testing on a semiconductor device using the memory mask to selectively mask certain results within the multiple scan chains. The results are associated with performance of LBIST testing on the semiconductor device.
摘要翻译： 在特定实施例中，公开了一种方法，其包括将多个扫描链内的故障比特位置映射到存储器掩码的存储器位置。 该方法还包括使用存储器掩模在半导体器件上执行逻辑内置自检（LBIST）测试，以选择性地掩盖多个扫描链中的某些结果。 结果与半导体器件上LBIST测试的性能相关。
-
公开(公告)号：US5597666A
公开(公告)日：1997-01-28
申请号：US821938
申请日：1992-01-14
申请人： Hong S. Kim
发明人： Hong S. Kim
CPC分类号： G03F1/29
摘要： The present invention relates to a method for fabrication of a mask capable of stabilizing the size and the thickness thereof.A method for fabrication of a mask according to the present invention comprises a step for successively depositing an oxide layer and a Cr layer on a quartz plate, a step for successively etching said oxide layer and said Cr layer by an E-beam, and a step for extending said oxide in volume by an oxidation process to form a phase-shifter.Therefore, the size and thickness of a mask can easily be controlled by using an oxide instead of PMMA of the photosensitive film as a phase-shifter and endurability of a mask can be improved.
摘要翻译： 本发明涉及一种能够稳定其尺寸和厚度的掩模的制造方法。 根据本发明的掩模的制造方法包括在石英板上连续地沉积氧化物层和Cr层的步骤，通过电子束连续蚀刻所述氧化物层和所述Cr层的步骤，以及 通过氧化处理体积扩展所述氧化物以形成移相器的步骤。 因此，通过使用氧化物代替感光性膜的PMMA作为移相器，可以容易地控制掩模的尺寸和厚度，并且可以提高掩模的耐久性。
-
公开(公告)号：US5159574A
公开(公告)日：1992-10-27
申请号：US798634
申请日：1991-11-26
申请人： Young H. Kim , Hong S. Kim
发明人： Young H. Kim , Hong S. Kim
CPC分类号： G11C8/18
摘要： The present invention provides an address transition detection circuit comprising inverting means (11 and G12 through G14) and a MOSFET's circuit which is composed of two cross-coupled MOSFET's (MN5 and MN6), first and second MOSFET's (MP2 and MP3) connected in series with each other, and third and fourth MOSFET's (MP4 and MP5) connected in series with each other, wherein the output lines of each inverter within the inverting means.
摘要翻译： 本发明提供一种地址转换检测电路，包括反相装置（11和G12至G14）和由两个交叉耦合的MOSFET（MN5和MN6）组成的MOSFET的电路，串联连接的第一和第二MOSFET（MP2和MP3） 彼此连接，并且第三和第四MOSFET（MP4和MP5）彼此串联连接，其中反相装置内的每个反相器的输出线。
-
公开(公告)号：US4292431A
公开(公告)日：1981-09-29
申请号：US156806
申请日：1980-06-05
申请人： Choong S. Kim , Kee J. Lee , Hong S. Kim , Yung B. Chae
发明人： Choong S. Kim , Kee J. Lee , Hong S. Kim , Yung B. Chae
IPC分类号： C07D233/54 , C07D233/64
CPC分类号： C07D233/64
摘要： This invention discloses a process for the production of hydroxymethylimidazoles which comprises reacting imidazolecarboxylic acids, their esters or inorganic salts with a formaldehyde agent in the presence of an alkali in an aqueous medium.
摘要翻译： 本发明公开了一种生产羟甲基咪唑的方法，包括使咪唑羧酸，其酯或无机盐与甲醛在碱存在下在水性介质中反应。
-
公开(公告)号：US07055135B2
公开(公告)日：2006-05-30
申请号：US10139568
申请日：2002-05-06
申请人： Hong S. Kim , Amit Majumdar , Sridhar Narayanan
发明人： Hong S. Kim , Amit Majumdar , Sridhar Narayanan
IPC分类号： G06F9/44
CPC分类号： G06F11/26
摘要： Embodiments of the present invention provide a method and apparatus for debugging an integrated circuit. In particular, one embodiment of the present invention includes steps of: (a) retrieving data from a design data base, and creating a design pattern in a pattern format, which design pattern includes stimulus data for stimuli to be applied to the integrated circuit and design response data for expected responses to the stimuli; (b) generating, responsive to the design pattern, a tester pattern and a test program for input to a tester; (c) testing the integrated circuit in the tester, responsive to the tester pattern and the test program, and generating a datalog that comprises test response data; and (d) generating a file, responsive to the datalog, wherein the test response data are reformatted into the pattern format.
-
-
-
-
-
-
-
-
-
搜索结果
23 条记录 (耗时 0.026 秒)
